Method, apparatus and system for wide metal line for SADP routing

1. An integrated circuit device, comprising:

at least one functional cell, wherein the functional cell has a default metal line width, and the functional cell comprises:

a first pair of wide metal formations comprising a first metal formation and a second metal formation placed about a first cell boundary of the functional cell, wherein both the first metal formation and the second metal formation have a width greater than the default metal line width and less than about five times the default metal line width, and the distance between the first metal formation and the second metal formation is equal to the default metal line width.

2. The integrated circuit device of claim 1 , wherein the first metal formation comprises a mandrel metal Metal-2 (M2) formation and wherein the second metal formation comprises a non-mandrel metal M2 formation.

3. The integrated circuit device of claim 2 , wherein the first and second metal formations are formed on a top edge and a bottom edge of the functional cell.

4. The integrated circuit device of claim 3 , wherein the first metal formation is on a top edge of the functional cell and the second metal formations is on a bottom edge of the functional cell.

5. The integrated circuit device of claim 1 , further comprising a second pair of wide metal formations comprising a third metal formation and a fourth metal formation placed about a second cell boundary of the functional cell.

6. The integrated circuit device of claim 5 , wherein the third metal formation comprises a mandrel metal M2 formation and wherein the fourth metal formation comprises a non-mandrel metal M2 formation.

7. The integrated circuit device of claim 5 , wherein the first wide pair is on the first cell boundary and the second wide pair is on the second cell boundary.

8. The integrated circuit device of claim 7 , wherein the first and second wide pairs are adapted to route high drive connections.

9. The integrated circuit device of claim 5 , wherein the functional cell has at least one 10 nm component and wherein the functional cell has a 8.75 track design.

10. The integrated circuit device of claim 9 , wherein:

the first metal formation has a width in the range of about 24 nm to about 120 nm;

the second metal formation has a width in the range of about 24 nm to about 120 nm;

the third metal formation has a width in the range of about 24 nm to about 120 nm; and

the fourth metal formation has a width in the range of about 24 nm to about 120 nm.

11. The integrated circuit device of claim 5 , further comprising alternating non-mandrel and mandrel metal formations between the first and second metal pairs.

12. A integrated circuit device, comprising:

at least a first functional cell and a second functional cell, each functional cell having a first pair of wide metal formations comprising a first metal formation and a second metal formation placed about a first cell boundary of the functional cell, wherein both functional cells have a common default metal line width, both the first metal formation and the second metal formation of each functional cell have a width greater than the default metal line width and less than about five times the default metal line width, and the distance between the first metal formation and the second metal formation of each functional cell is equal to the default metal line width; and

a wide M2 metal formation providing an interconnection between the first and second functional cells, wherein the interconnection comprises a first M3 metal formation connected to the M2 metal formation and a portion of the first functional cell and a second M3 metal formation connected to the M2 formation and a portion of the second functional cell.

13. The integrated circuit device of claim 12 , wherein:

the first and second functional cells each comprise at least one 10 nm component and a 8.75 track design.

14. The integrated circuit device of claim 12 , wherein:

the M2 metal formation has a width in the range of about 24 nm to about 120 nm.

15. The integrated circuit device of claim 12 , wherein:

the interconnection comprises a plurality of vias to connect the first and second M3 metal formations to the M2 formation and to the first and second functional cells.

16. An integrated circuit device, comprising:

at least one cell, wherein the cell has a default metal line width, and the cell comprises:

a first pair of wide metal formations comprising a first metal formation and a second metal formation placed about a first cell boundary of the cell, wherein both the first metal formation and the second metal formation have a width greater than the default metal line width and less than about five times the default metal line width, and the distance between the first metal formation and the second metal formation is equal to the default metal line width.

17. The integrated circuit device of claim 16 , wherein the first metal formation comprises a mandrel metal Metal-2 (M2) formation and wherein the second metal formation comprises a non-mandrel metal M2 formation.

18. The integrated circuit device of claim 16 , wherein the first and second metal formations are formed on a top edge and a bottom edge of the cell.

19. The integrated circuit device of claim 16 , wherein the first metal formation is on a top edge of the cell and the second metal formation is on a bottom edge of the cell.

20. The integrated circuit device of claim 16 , further comprising a second pair of wide metal formations comprising a third metal formation and a fourth metal formation placed about a second cell boundary of the cell.