ESD placement in semiconductor device

1. An apparatus comprising:

a first power ESD protection circuit arranged in a first circuit area;

a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction;

a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits;

a plurality of first power terminals arranged in the second circuit area; and

a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

2. The apparatus of claim 1 , further comprising a second power ESD protection circuit arranged in a third circuit area,

wherein the second circuit area is arranged between the first and third circuit areas in the first direction, and

wherein the first power line further couples the plurality of first power terminals to the second power ESD protection circuit.

3. The apparatus of claim 2 , further comprising:

a plurality of second power terminals arranged in the second circuit area; and

a second power line extending in the first direction, the second power line coupling the plurality of second power terminals to the first and second power ESD protection circuits.

4. The apparatus of claim 3 , wherein the plurality of data I/O terminals are located between the plurality of first power terminals and the plurality of second power terminals in a second direction substantially perpendicular to the first direction.

5. The apparatus of claim 4 , wherein an array pitch of the first and second power terminals of the first and second plurality of power terminals in the second direction is substantially the same as a width of each of the plurality of data I/O circuits in the second direction.

6. The apparatus of claim 1 , further comprising a third power line coupling the first power line to an internal circuit.

7. The apparatus of claim 6 , wherein the first power line is lower in resistance than the third power line.

8. The apparatus of claim 1 , wherein each of the plurality of data I/O terminals overlaps with the associated one of the plurality of data I/O circuits.

9. The apparatus of claim 8 , wherein each of the plurality of first power terminals overlaps with two of the data I/O circuits of the plurality of data I/O circuits.

10. The apparatus of claim 1 , wherein the data I/O terminals of the plurality of data I/O terminals and first power terminals of the plurality of first power terminals are arranged so as not to overlap with the data I/O circuits.

11. The apparatus of claim 1 , wherein each of the plurality of data I/O circuits includes:

a parallel-serial conversion circuit;

a serial-parallel conversion circuit;

a data input buffer coupled between an associated one of the plurality of data I/O terminals and the parallel-serial conversion circuit; and

a data output buffer coupled between an associated one of the plurality of data I/O terminals and the serial-parallel conversion circuit.

12. An apparatus comprising:

a plurality of external terminals including a plurality of data I/O terminals, a plurality of first power terminals and a plurality of second power terminals;

a plurality of data I/O circuits each coupled to a corresponding one of the plurality of data I/O terminals, a corresponding at least one of the plurality of first power terminals and a corresponding at least one of the plurality of second power terminals; and

first and second ESD protection circuits each coupled to at least one of the plurality of first power terminals and at least one of the plurality of second power terminals;

wherein the plurality of external terminals and the plurality of data I/O circuits are arranged in a first circuit area; and

wherein the first ESD protection circuit and the second ESD protection circuit are arranged in a second circuit area and a third circuit area, respectively, and the first circuit area is between the second circuit area and the third circuit area.

13. The apparatus of claim 12 ,

wherein the first ESD protection circuit includes first and second circuit blocks,

wherein the second ESD protection circuit includes third and fourth circuit blocks,

wherein the plurality of first power terminals are coupled to the first and third circuit blocks, and

wherein the plurality of second power terminals are coupled to the second and fourth circuit blocks.

14. The apparatus of claim 13 , further comprising:

a first conductive line coupling the plurality of first power terminals to the first and third circuit blocks in common; and

a second conductive line coupling the plurality of second power terminals to the second and fourth circuit blocks in common.

15. The apparatus of claim 14 ,

wherein the first circuit area is arranged between the second circuit area and the third circuit area in a first direction,

wherein the plurality of first power terminals are arranged in the first direction,

wherein the plurality of second power terminals are arranged in the first direction, and

wherein each of the first and second conductive lines extends in the first direction.

16. The apparatus of claim 15 , wherein one of the plurality of data I/O terminals, one of the plurality of first power terminals, and one of the plurality of second power terminals are arranged in a second direction substantially perpendicular to the first direction.

17. The apparatus of claim 16 , wherein one of the plurality of data I/O terminals is arranged between one of the plurality of first power terminals and one of the plurality of second power terminals.

18. An apparatus comprising:

a plurality of power terminals and a plurality of data I/O terminals alternately arranged in a first direction;

a plurality of data I/O circuits arranged in the first direction, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits;

first and second circuit areas each including a plurality of power ESD protection circuits, the first and second circuit areas being arranged so as to sandwich the plurality of data I/O circuits in a second direction different from the first direction; and

a plurality of first power lines extending in the second direction and the plurality of first power lines coupled to the plurality of power ESD protection circuits in the first and second circuit areas, each of the plurality of first power lines being coupled to an associated one of the plurality of power terminals.

19. The apparatus of claim 18 , wherein the plurality of power terminals and the plurality of data I/O terminals overlap with the plurality of data I/O circuits.

20. The apparatus of claim 18 , further comprising a plurality of second power lines coupling each of the plurality of first power lines to internal circuits,

wherein each of the plurality of first power lines is lower in resistance than each of the plurality of second power lines.