Device integration schemes leveraging a bulk semiconductor substrate having a <111 > crystal orientation

1. A structure comprising:

a bulk semiconductor substrate comprising a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation, the bulk semiconductor substrate having a first device region and a second device region;

a first CMOS transistor in the single-crystal semiconductor material of the first device region of the bulk semiconductor substrate; and

a non-CMOS transistor in the second device region of the bulk semiconductor substrate, the non-CMOS transistor including a layer stack on the single-crystal semiconductor material of the bulk semiconductor substrate, and the layer stack including a layer comprising a III-V compound semiconductor material.

2. The structure of claim 1 wherein the single-crystal semiconductor material is single-crystal silicon.

3. The structure of claim 1 wherein the III-V compound semiconductor material is gallium nitride.

4. The structure of claim 1 wherein the III-V compound semiconductor material of the layer stack has a crystal structure that is substantially single crystal.

5. The structure of claim 1 wherein the bulk semiconductor substrate has a top surface, and the first CMOS transistor is a field-effect transistor including a source/drain region positioned in the bulk semiconductor substrate at least in part beneath the top surface.

6. The structure of claim 5 wherein the bulk semiconductor substrate has a third device region comprising the single-crystal semiconductor material, and further comprising:

a bipolar junction transistor in the third device region of the bulk semiconductor substrate, the bipolar junction transistor including a terminal positioned in the bulk semiconductor substrate at least in part beneath the top surface.

7. The structure of claim 1 wherein the bulk semiconductor substrate has a top surface, and the first CMOS transistor is a bipolar junction transistor including a terminal positioned in the bulk semiconductor substrate at least in part beneath the top surface.

8. The structure of claim 1 wherein the bulk semiconductor substrate has a third device region comprising the single-crystal semiconductor material, and further comprising:

a second CMOS transistor in the third device region of the bulk semiconductor substrate,

wherein the first CMOS transistor and the second CMOS transistor are different transistor types.

9. The structure of claim 1 wherein the bulk semiconductor substrate has a top surface, and the layer stack is positioned on the top surface of the bulk semiconductor substrate.

10. The structure of claim 9 wherein the top surface of the bulk semiconductor substrate is planar in the first device region and in the second device region, and the first CMOS transistor includes a device layer positioned on the top surface of the bulk semiconductor substrate.

11. The structure of claim 1 wherein the bulk semiconductor substrate has a first surface and a trench extending from the first surface into the bulk semiconductor substrate, and the layer stack is positioned on the bulk semiconductor substrate inside the trench.

12. The structure of claim 11 wherein the bulk semiconductor substrate has a second surface at a bottom of the trench, and the layer stack is positioned on the second surface.

13. The structure of claim 11 further comprising:

a shallow trench isolation region in the bulk semiconductor substrate, the shallow trench isolation region laterally positioned between the first device region and the second device region,

wherein the trench extends to a greater depth into the bulk semiconductor substrate relative to the first surface than the shallow trench isolation region.

14. The structure of claim 11 wherein the trench includes a plurality of sidewalls, and further comprising:

a spacer on each of the plurality of sidewalls, the spacer comprised of a dielectric material.

15. The structure of claim 1 further comprising:

an interconnect structure positioned over the bulk semiconductor substrate, the interconnect structure including a first plurality of contacts coupled to the first CMOS transistor and a second plurality of contacts coupled to the non-CMOS transistor.

16. The structure of claim 1 further comprising:

a shallow trench isolation region in the bulk semiconductor substrate, the shallow trench isolation region laterally positioned between the first device region and the second device region.

17. A method comprising:

providing a bulk semiconductor substrate comprising a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation;

forming a CMOS transistor in a first device region of the bulk semiconductor substrate, wherein the first device region comprises the single-crystal semiconductor material;

forming a layer stack including a layer comprising a III-V compound semiconductor material in a second device region of the bulk semiconductor substrate, wherein the second device region comprises the single-crystal semiconductor material; and

forming a non-CMOS transistor using the layer stack.

18. The method of claim 17 wherein the single-crystal semiconductor material is single-crystal silicon, and the III-V compound semiconductor material is gallium nitride.

19. The method of claim 17 further comprising:

forming a trench extending from a first surface into the bulk semiconductor substrate to a second surface at a bottom of the trench,

wherein the layer stack is positioned on the second surface of the bulk semiconductor substrate inside the trench.

20. The method of claim 17 further comprising:

forming a shallow trench isolation region in the bulk semiconductor substrate,

wherein the shallow trench isolation region is laterally positioned between the first device region and the second device region.