IP Library Granted Patent US 11,410,986
Granted Patent B2
US 11,410,986 · App. 17/075,968 · Granted Aug 9, 2022

Power cell for semiconductor devices

Inventors: Chung-Chieh Yang (Zhubei, TW); Chung-Ting Lu (Kaohsiung, TW); Yung-Chow Peng (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L27/0207H01L21/76885H01L21/823871H01L23/5226
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Quick Facts
Patent No.
US 11,410,986
App. No.
17/075,968
Granted
Aug 9, 2022
Kind
B2
Abstract

A semiconductor device includes an electrical circuit having a first set of circuit elements, wherein the electrical circuit is in a circuit area on a first side of a substrate, and a first set of conductive pillars over the first side of the substrate. In the semiconductor device, a first conductive rail electrically connects to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail; and a first power cell extending through the substrate, wherein the first power cell includes a first number of power pillars extending through the substrate, wherein each of the first number of power pillars electrically connects to the first conductive rail in parallel.

Claims (58)

1. A device, comprising:

an electrical circuit having a first set of circuit elements, wherein the electrical circuit is in a circuit area on a first side of a substrate;

a first set of conductive pillars over the first side of the substrate;

a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail; and

a first power cell extending through the substrate, wherein the first power cell comprises:

a first number of power pillars extending through the substrate, wherein each of the first number of power pillars is electrically connected to the first conductive rail in parallel.

2. The device of claim 1 , further comprising:

a second conductive rail over the first side of the substrate;

a second set of conductive pillars, wherein each of the second set of conductive pillars is electrically connected to the second conductive rail; and

a second power cell comprising

a second number of power pillars extending through the substrate, wherein the second conductive rail electrically connects the second number of power pillars in parallel.

3. The device of claim 2 , wherein a number of the first number of power pillars is equal to a number of the second number of power pillars.

4. The device of claim 2 , wherein a number of the first number of power pillars is different from a number of the second number of power pillars.

5. The device of claim 2 , wherein the first conductive rail electrically connects to ground and the second conductive rail electrically connects to a supply voltage.

6. The device of claim 2 , wherein the first power cell is adjacent to the second power cell.

7. The device of claim 2 , wherein

the circuit area is between the first power cell and

the second power cell.

8. The device of claim 7 , further comprising:

a third conductive rail below a second side of the substrate, wherein the second power cell electrically connects to the third conductive rail below the second side of the substrate.

9. The device of claim 1 , wherein the first power cell is separated from the circuit area by a first separation distance of

not less than 0.001 μm and

not more than 200 μm.

10. A semiconductor device, comprising

a transistor region at a first side of a substrate;

a plurality of transistors in the transistor region;

a first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to a corresponding transistor of the plurality of transistors;

a first conductive rail electrically connected to each of the first set of conductive pillars, wherein the first conductive rail is on the first side of the substrate;

a second conductive rail, wherein the second conductive rail is on a second side of the substrate, and the second side of the substrate is opposite the first side of the substrate; and

a first number of power pillars in a power cell of a first power cell region of the substrate, wherein

each of the first number of power pillars is electrically connected to the first conductive rail, and

each of the first number of power pillars is electrically connected to the second conductive rail.

11. The semiconductor device of claim 10 , further comprising a region between the transistor region and the first power cell region, wherein the region has a width ranging from not less than 0.001 μm to not more than 200 μm.

12. The semiconductor device of claim 10 , wherein the first conductive rail electrically connects to a source of each transistor of the plurality of transistors.

13. The semiconductor device of claim 10 , wherein a number of the first number of power pillars is not more than 1000.

14. The semiconductor device of claim 10 , further comprising a second power region with a second number of power pillars electrically connected to the first number of power pillars by the first conductive rail.

15. The semiconductor device of claim 10 , further comprising:

a second number of power pillars in the power cell, wherein

the first number of power pillars are

in a first portion of the power cell, and

the second number of power pillars are

in a second portion of the power cell, and

electrically connect to a second voltage source; and

a second conductive rail electrically connected to the second number of power pillars.

16. The semiconductor device of claim 15 , further comprising:

a dummy region at a corner of the transistor region, wherein the dummy region comprises power pillars which are electrically isolated from the second voltage source or the transistor region.

17. A method of making a semiconductor device, comprising:

doping a plurality of active areas in a circuit area of a substrate;

manufacturing a power pillar extending through the substrate;

manufacturing a plurality of conductive pillars extending from the substrate, wherein each of the plurality of conductive pillars is electrically connected to a corresponding active area of the plurality of active areas; and

manufacturing a first conductive rail extending from over the circuit area to the power pillar, wherein the first conductive rail electrically connects the power pillar to each of the plurality of conductive pillars.

18. The method of claim 17 , wherein manufacturing the power pillar comprises:

etching an opening through the substrate;

filling the opening with a conductive material; and

manufacturing, on a first side of the substrate, a plurality of conductive vias and a plurality of conductive lines extending from the conductive material in the opening, wherein the plurality of conductive pillars are on the first side of the substrate.

19. The method of claim 18 , wherein manufacturing the power pillar further comprises:

manufacturing a plurality of backside power pillars on a second side of the substrate opposite the first side of the substrate.

20. The method of claim 19 , further comprising manufacturing a second conductive rail, wherein the second conductive rail electrically connects each the plurality of backside power pillars in parallel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2020
From: YANG, CHUNG-CHIEH; LU, CHUNG-TING; PENG, YUNG-CHOW
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 054286/0193 →
Continuity (1)
Related Publication 20220122960A1 · Apr 21, 2022
Cited By (1)
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