Systems and methods for flexible motherboard supporting flexible processor utilization for optimized design
An information handling system may include a processor; a memory; a voltage regulator module (VRM) coupled to the processer and a power source; an embedded controller (EC) operatively coupled to the VRM; the power source to provide power to the processor based on the type of processor detected, memory, and EC; and the EC being operatively coupled to a switch that is operatively coupled to a resistor divider circuit for setting a load line resistance level to the VRM; and the EC and to transmit a signal to the switch to set a load line resistance level provided to the VRM, via adjustment to the resistor divider circuit, the adjustment based on power requirements of the type of processor installed as detected by a basic input/output system (BIOS).
1. An information handling system with a flexible motherboard system, comprising:
a processor;
a memory;
a voltage regulator module (VRM) coupled to the processer and a power source;
an embedded controller (EC) operatively coupled to the VRM to execute code to correlate detecting a first type of processor installed with a load line resistance level to allow for installation or upgrade among plural types of processors;
the power source to provide power to the first type of processor, memory, and EC; and
the EC being operatively coupled to a switch that is operatively coupled to a resistor divider circuit comprising a first resistor and a second resistor for setting a load line resistance level to the VRM in a first switched state; and
a general-purpose input/output (GPIO) input pin operatively coupled between the EC and the switch to transmit a signal from the EC to switch the switch to set the load line resistance level provided to the VRM based on power requirements of the first type of processor installed as detected by a basic input/output system (BIOS).
2. The information handling system of claim 1 , further comprising the BIOS to, via an IA32 CPUID instruction set, identify to the EC the presence of the first type of processor within the information handling system for the EC to define the resistance level for output of the GPIO to the switch to control the load line resistance level for the first type of processor.
3. The information handling system of claim 1 , further comprising the VRM placed intermediary to the processor and the switch to:
regulate power levels to the processor under varying loads; and
adjust the regulated power level based on load line resistance levels according to the operation of the resistor divider and switch for the first type of detected processer.
4. The information handling system of claim 1 , further comprising a third resistor of the resistor divider operatively coupled to the switch and activated to adjust the load line resistance level setting associated with a second type of processor detected by a BIOS of the information handling system in a second switched state.
5. The information handling system of claim 1 , wherein the resistor divider defines a default load line resistance level setting associated with the first type of processor.
6. The information handling system of claim 1 , wherein the signal from the EC to reset the load line resistance level further directs a VRM placed intermediary to the first processor and the switch to be powered down before adjusting the load line resistance level.
7. The information handling system of claim 1 wherein the switch includes a metal-oxide-semiconductor field-effect transistor (MOSFET) for adjusting the load line resistor level setting via adjustment to the resistor divider.
8. A method of modifying a load line setting associated with a processor of an information handling system with a flexible motherboard system, comprising:
initiating power at the information handling system to power the processor, a voltage regulator module (VRM), a memory, and an embedded controller (EC);
with execution of a basic input/output system (BIOS), detecting a first type of processor within the information handling system from among a plurality of candidate types of processors;
accessing a table maintained in the memory, via the EC executing code instructions, to determine a load line setting to be associated with the first type of processor detected as installed in the information handling system; and
where the load line setting to be associated with the first type of processor is to be changed:
powering down the processor and VRM;
with the EC, via a general-purpose input/output (GPIO) output pin, transmitting a signal to a switch operatively coupled to the EC and the VRM, the EC to switch the switch with the signal to set a load line resistance level provided to the VRM based on power requirements of the first type of processor installed as detected by the basic input/output system (BIOS); and
with the switch, adjusting a resistor divider coupled to the switch to set the load line resistance level provided to the VRM based on power requirements of the first type of processor installed as detected by the basic input/output system (BIOS).
9. The method of claim 8 , further comprising:
regulating power levels with the VRM to the processor under varying loads; and
adjusting the regulated power level based on load line resistance levels to the VRM according to the operation of the resistor divider and switch for the first type of detected processer.
10. The method of claim 8 further comprising:
with the basic input/output system (BIOS) detecting the first type of the processor via an IA32 CPUID instruction set.
11. The method of claim 8 further comprising:
a resistor divider including a first resistor and a second resistor; and
adjusting the resistor divider includes adjusting a number of resistors coupled to the resistor divider includes operatively coupling a third resistor in parallel to the second resistor via the switch to adjust the load line resistance level to the VRM.
12. The method of claim 8 further comprising:
setting a first load line resistance level to the first type of processor using a first configuration of resistors forming the resistor divider; and
setting a second load line resistance level to a second type of processor using a second configuration of resistors forming the resistor divider.
13. The method of claim 8 , wherein the switch includes a metal-oxide-semiconductor field-effect transmitter (MOSFET) to adjust the resistor divider.
14. A method of switching load line settings for modulating power to a processor installed in a flexible motherboard system, comprising:
detecting the presence of a first type of processor installed in the flexible motherboard from a plurality of candidate types of processors via executing a basic input/output system (BIOS) within an information handling system;
providing a default load line setting to a switch in a first switched state via a signal from an embedded controller (EC), the default load line setting determining a first load line resistance level to be provided to the VRM powering the first type of processor, the first load line resistance level set by the switch controlling a resistor divider including a first resistor and a second resistor;
detecting, via execution of the BIOS, the presence of a second type of processor subsequent to a reboot of the information handling system;
providing a secondary load line setting to the switch by a signal from the EC to switch the switch to a second switched state, the secondary load line setting determining a second load line resistance level to be provided to the VRM powering the second type of processor, the second load line resistance level set by the switch controlling the resistor divider including the first resistor, the second resistor, and a third resistor in parallel with the second resistor in the resistor divider.
15. The method of claim 14 further comprising:
executing an IA32 CPUID instruction set by the BIOS to detect the presence of the first type of processor or the second type of processor.
16. The method of claim 14 further comprising:
the first resistor and the second resistor placed in series to set the first load line resistance level.
17. The method of claim 14 further comprising:
providing the default load line setting to the switch and providing the secondary load line setting to the switch via a via a general-purpose input/output (GPIO) output pin on the EC.
18. The method of claim 14 further comprising:
powering off the VRM prior to providing the secondary load line setting to the switch.
19. The method of claim 14 , wherein the switch comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) operatively coupled to the resistor divider and is placed intermediate to the EC and the VRM.
20. The method of claim 14 further comprising:
providing a third load line setting by adjusting the resistor divider to include a fourth resistor in parallel with the second resistor in the resistor divider via the switch to adjust the load line resistance level to the VRM to a third load line resistance level.