Probabilistic shaping techniques for high performance coherent optical transceivers
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
1. A transmitter device comprising a distribution matcher encoder module including n encoder function devices coupled in series, the series of n encoder function devices being configured to convert data from a first form (x) to a second form (b), wherein the series of n encoder function devices is configured to:
receive data x, a code length n, and a bits per codeword n′ as inputs;
store the following initial values: a n =x and n n ′=n′;
perform the following actions for i=n−1 to 0
when a first condition characterized by
a
i
+
1
≥
(
i
n
i
+
1
′
-
1
)
or a second condition characterized by n i+1′≤ 0 is satisfied, compute and store the following intermediate values:
a
i
=
a
i
+
1
-
(
i
n
i
+
1
′
-
1
)
,
b i =0, and n i ′=n i+1 , and
when neither the first condition nor the second condition is satisfied, compute and store the following intermediate values: a i =a i+1 , b i =1, and n i ′=n i+1 ′−1; and
output converted data b.
2. The transmitter device of claim 1 , wherein each of the n encoder function devices comprises one or more carry save adders.
3. The transmitter device of claim 1 , further comprising a splitter module electrically coupled to the distribution matcher encoder module and configured to receive data.
4. The transmitter device of claim 3 , further comprising a forward error correction (FEC) encoder module electrically coupled to the splitter module and the distribution matcher encoder module.
5. The transmitter device of claim 4 , further comprising a mapper module electrically coupled to the FEC encoder module.
6. The transmitter device of claim 1 ; wherein the series of n encoder function devices includes a plurality of encoder storage units configured to store the initial values and the intermediate values.
7. The transmitter device of claim 1 , wherein the series of n encoder function devices includes encoder comparison and adder circuits configured to perform the actions for i=n−1 to 0.
8. A transmitter device comprising a distribution matcher encoder module including n encoder function devices coupled in series, the series of n encoder function devices being configured to convert data from a first form (x) to a second form (b) using an encoder lookup table (LUT), wherein the series of n encoder function devices is configured to:
receive data x, a code length n, and a bits per codeword n′ as inputs;
store the following initial values: a n =x and n n ′=n′;
perform the following actions for i=n−1 to 0
when a first condition characterized by a i+1 ≥t i [n i+1′− 1] or a second condition characterized by n i+1 ′≤0 is satisfied, compute and store the following intermediate values: a i =a i+1 −t i [n i+1′− 1], b i =0, and n i ′=n i+1 ′, where t i [n] is the function to access the encoder LUT, and
when neither the first condition nor the second condition is satisfied, compute and store the following intermediate values: a i =a i+1 , b i =1, and n i ′=n i+1 −1; and
output converted data b.
9. The transmitter device of claim 8 , wherein each of the n encoder function devices comprises one or more carry save adders.
10. The transmitter device of claim 8 , further comprising a splitter module electrically coupled to the distribution matcher encoder module and configured to receive data.
11. The transmitter device of claim 10 , further comprising a forward error correction (FEC) encoder module electrically coupled to the splitter module and the distribution matcher encoder module.
12. The transmitter device of claim 11 , further comprising a mapper module electrically coupled to the FEC encoder module.
13. The transmitter device of claim 8 , wherein the series of n encoder function devices includes a plurality of encoder storage units configured to store the initial values and the intermediate values.
14. The transmitter device of claim 8 , wherein the series of n encoder function devices includes encoder comparison and adder circuits configured to perform the actions for i=n−1 to 0.
15. A transmitter device comprising a distribution matcher encoder module including n encoder function devices coupled in series, the series of n encoder function devices being configured to convert data from a first form (x) to a second form (b) using an encoder lookup table (LUT), wherein the series of n encoder function devices is configured to:
receive data x and a code length n as inputs;
store the following initial value: n′=0;
while
(
x
≥
(
n
n
′
)
)
compute and store the following intermediate value:
x
=
x
-
(
n
n
′
)
,
and
compute and store the following intermediate value: n′=n′+1;
compute and store the following intermediate value: a n =x;
perform the following actions for i=n−1 to 0:
when a first condition characterized by a i+1 ≥t i [n i+1′− 1] or a second condition characterized by n′≤0 is satisfied, compute and store the following intermediate values: a i =a i+1 −t i [n′−1] and b i =0, where t i [n] is the function to access the encoder LUT, and
when neither the first condition nor the second condition is satisfied,compute and store the following intermediate values: a i =a i+1 , b i =1, and n′=n′−1; and
output converted data b.
16. The transmitter device of claim 15 , wherein each of the n encoder function devices comprises one or more carry save adders.
17. The transmitter device of claim 15 , further comprising a splitter module electrically coupled to the distribution matcher encoder module and configured to receive data.
18. The transmitter device of claim 17 , further comprising a forward error correction (FEC) encoder module electrically coupled to the splitter module and the distribution matcher encoder module.
19. The transmitter device of claim 18 , further comprising a mapper module electrically coupled to the FEC encoder module and a channel module.
20. The transmitter device of claim 15 , wherein the series of n encoder function devices includes a plurality of encoder storage units configured to store the initial values and the intermediate values.
21. The transmitter device of claim 15 , wherein the series of n encoder function devices includes encoder comparison and adder circuits configured to perform the actions while
(
x
≥
(
n
n
′
)
)
and the actions for i=n−1 to 0.