IP Library Granted Patent US 11,114,505
Granted Patent B2
US 11,114,505 · App. 17/078,440 · Granted Sep 7, 2021

Imaging device

Inventors: Shunsuke Isono (Osaka, JP); Hidenari Kanehara (Kyoto, JP); Sanshiro Shishido (Osaka, JP); Takeyoshi Tokuhara (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L27/307H01L27/14605H01L27/14607H01L27/14636H01L27/14665H04N5/374H04N5/376H01L27/14603H01L27/14612H01L27/14621H01L27/14623H01L27/14627H01L27/14643
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Quick Facts
Patent No.
US 11,114,505
App. No.
17/078,440
Granted
Sep 7, 2021
Kind
B2
Abstract

An imaging device including a semiconductor substrate including a pixel region and a peripheral region; an insulating layer covering the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer covering the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry electrically connected to the first electrodes; peripheral circuitry electrically connected to the detection circuitry, and; and a third electrode located on the insulating layer. The second electrode includes a connection region in which the second electrode is connected to third electrode, the connection region overlaps analog circuitry in a plan view, and in any cross-sections perpendicular to a surface of the semiconductor substrate and parallel to a column or row direction and that intersects at least one of the first electrodes, the digital circuitry includes no transistor that is located directly below the connection region.

Claims (50)

1. An imaging device comprising:

a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;

an insulating layer that covers the pixel region and the peripheral region;

first electrodes located on the insulating layer above the pixel region and arranged two-dimensionally in a column direction and a row direction;

a photoelectric conversion layer that covers the first electrodes;

a second electrode that covers the photoelectric conversion layer;

detection circuitry located in the pixel region and configured to be electrically connected to the first electrodes;

peripheral circuitry located in the peripheral region, configured to be electrically connected to the detection circuitry, and including analog circuitry and digital circuitry; and

a third electrode located on the insulating layer above the peripheral region, wherein

the second electrode extends above the peripheral region,

the second electrode includes a connection region in which the second electrode is connected to third electrode,

the connection region overlaps the analog circuitry in a plan view, and

in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the connection region, no transistor of the digital circuitry is located directly below the connection region.

2. The imaging device according to claim 1 , wherein

the peripheral circuitry includes a wire connected between the analog circuitry and the digital circuitry, and

the connection region overlaps the wire in the plan view.

3. The imaging device according to claim 1 , wherein

the peripheral circuitry includes a wire for connecting the analog circuitry to external circuitry, and

the connection region overlaps the wire in the plan view.

4. The imaging device according to claim 1 , wherein

the second electrode includes, above the peripheral region, a first region in which the photoelectric conversion layer is not present between the second electrode and the insulating layer, and

the first region includes the connection region and a non-connection region other than the connection region.

5. The imaging device according to claim 4 , wherein in the column direction or the row direction, the non-connection region has a length that is greater than a length of the connection region.

6. The imaging device according to claim 1 , wherein in the plan view, the second electrode has an area that is larger than an area of the pixel region.

7. An imaging device comprising:

a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;

an insulating layer that covers the pixel region and the peripheral region;

first electrodes located on the insulating layer above the pixel region and arranged two-dimensionally in a column direction and a row direction;

a photoelectric conversion layer that covers the first electrodes;

a second electrode that covers the photoelectric conversion layer;

detection circuitry located in the pixel region and configured to be electrically connected to the first electrodes;

peripheral circuitry located in the peripheral region, configured to be electrically connected to the detection circuitry, and including analog circuitry and digital circuitry; and

a third electrode located on the insulating layer above the peripheral region, wherein

the second electrode extends above the peripheral region,

the second electrode includes a connection region in which the second electrode is connected to third electrode,

the connection region overlaps the digital circuitry in a plan view, and

in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the connection region, no transistor of the analog circuitry is located directly below the connection region.

8. The imaging device according to claim 7 , wherein

the peripheral circuitry includes a wire connected between the analog circuitry and the digital circuitry, and

the connection region overlaps the wire in the plan view.

9. The imaging device according to claim 7 , wherein

the peripheral circuitry includes a wire for connecting the analog circuitry to external circuitry, and

the connection region overlaps the wire in the plan view.

10. The imaging device according to claim 7 , wherein

the second electrode includes, above the peripheral region, a first region in which the photoelectric conversion layer is not present between the second electrode and the insulating layer, and

the first region includes the connection region and a non-connection region other than the connection region.

11. The imaging device according to claim 10 , wherein in the column direction or the row direction, the non-connection region has a length that is greater than a length of the connection region.

12. The imaging device according to claim 7 , wherein in the plan view, the second electrode has an area that is larger than an area of the pixel region.

13. The imaging device according to claim 1 , wherein in a cross-section perpendicular to the surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, the analog circuitry includes a transistor that is located directly below the connection region.

14. The imaging device according to claim 7 , wherein in a cross-section perpendicular to the surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, the digital circuitry includes a transistor that is located directly below the connection region.

Priority Claims (1)
JP JP2018-008575 · Jan 23, 2018 · national
Continuity (2)
Continuation 16251599 · Jan 18, 2019
Related Publication 20210043688A1 · Feb 11, 2021
Cited By (1)
US 12,495,634