Neural network inference accelerator based on one-time-programmable (OTP) memory arrays with one-way selectors
The disclosed embodiments provide neural network inference accelerator based on one-time-programmable (OTP) memory arrays with one-way selectors. In some embodiments, a memory array may comprise: a plurality of one-time-programmable memory cells each comprising: a one-time-programmable memory element; a top electrode having an upper surface in contact with the one-time-programmable memory element; a dielectric layer in contact with a lower surface of the top electrode; a bottom electrode; and a dense layer having an upper surface in contact with the dielectric layer, and a lower surface in contact with the bottom electrode, wherein the dense layer comprises Al 2 O 3 or MgO.
1. A memory array comprising:
a plurality of one-time-programmable (OTP) memory cells each comprising:
a OTP memory element;
a top electrode having an upper surface in contact with the one-time-programmable memory element;
a dielectric layer in contact with a lower surface of the top electrode;
a bottom electrode; and
a dense layer having an upper surface in contact with the dielectric layer and a lower surface in contact with the bottom electrode, wherein the dense layer includes at least one of Al 2 O 3 or MgO.
2. The memory array of claim 1 , wherein the top electrode includes doped Ag.
3. The memory array of claim 1 , wherein the top electrode includes alloyed Ag.
4. The memory array of claim 1 , wherein the bottom electrode includes an inert metal.
5. The memory array of claim 1 , wherein the one-time-programmable memory element includes a two-terminal resistive OTP memory element.
6. The memory array of claim 5 , wherein the two-terminal resistive OTP memory element is based on at least one of oxide breakdown, metal injection, or fuse/anti-fuse.
7. The memory array of claim 1 , further comprising:
a plurality of word lines, wherein each top electrode of the one-time-programmable memory cells is electrically coupled to at least one of the word lines; and
a plurality of bit lines, wherein each bottom electrode of the one-time-programmable memory cells is electrically coupled to at least one of the bit lines.
8. A neural network comprising:
the memory array of claim 7 , wherein each of the OTP memory cells of the memory array is programmed with a respective weight;
a peripheral input circuitry configured to apply respective voltages to the word lines of the memory array; and
a peripheral output circuitry configured to measure respective currents from the bit lines of the memory array.
9. The neural network of claim 8 , wherein the neural network is configured to perform Multiplication and Accumulation operations.
10. A device comprising:
a one-time-programmable memory element;
a top electrode including Ag;
a bottom electrode;
a dielectric layer in contact with the top electrode; and
a dense layer having an upper surface in contact with the dielectric layer and a lower surface in contact with the bottom electrode, wherein the dense layer includes at least one of Al 2 O 3 or MgO.
11. The device of claim 10 , wherein the top electrode is includes doped Ag.
12. The device of claim 10 , wherein the top electrode is includes alloyed Ag.
13. The device of claim 10 , wherein the bottom electrode includes an inert metal.
14. The device of claim 13 , wherein the inert metal is includes Pt or Pd.
15. A one-time-programmable (OTP) memory cell comprising:
a OTP memory element;
a top electrode having an upper surface in contact with the OTP memory element;
a dielectric layer in contact with a lower surface of the top electrode;
a bottom electrode; and
a dense layer having an upper surface in contact with the dielectric layer and a lower surface in contact with the bottom electrode, wherein the dense layer includes at least one of Al 2 O 3 or MgO.
16. The OTP memory cell of claim 15 , wherein the top electrode includes doped Ag.
17. The OTP memory cell of claim 15 , wherein the top electrode includes alloyed Ag.
18. The OTP memory cell of claim 15 , wherein the bottom electrode includes an inert metal.
19. The OTP memory cell of claim 15 , wherein the OTP memory element includes a two-terminal resistive OTP memory element.
20. The OTP memory cell of claim 19 , wherein the two-terminal resistive OTP memory element is based on at least one of oxide breakdown, metal injection, or fuse/anti-fuse.