Voltage droop reduction with a secondary power supply
A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.
1. A droop reduction circuit on a die comprising:
a voltage detector circuit to detect voltage droop in a supply voltage received by a first load;
a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop; and
the PSH banks, each of which includes at least one power switch having an input terminal to receive a secondary voltage which is higher than the supply voltage and is received by a second load on the die, a gate terminal to receive a drive signal from the driver controller, and an output terminal to pull up the voltage droop in the supply voltage, wherein the driver controller circuit includes N slice circuits connected to each other via a parallel connection and a series connection, wherein an input via the parallel connection to the N slice circuits causes the N slice circuits to output N drive signals in parallel, and a delay input via the series connection to the N slice circuits causes the N slice circuits to output the N drive signals sequentially, N being the number of the PSH banks.
2. A droop reduction circuit on a die comprising:
a voltage detector circuit to detect voltage droop in a supply voltage received by a first load;
a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop; and
the PSH banks, each of which includes at least one power switch having an input terminal to receive a secondary voltage which is higher than the supply voltage and is received by a second load on the die, a gate terminal to receive a drive signal from the driver controller, and an output terminal to pull up the voltage droop in the supply voltage, wherein the driver controller circuit includes a delay chain of M multiplexers which provides a delay time length controlled by a configurable M-bit one-hot code containing at most one non-zero bit.
3. The droop reduction circuit of claim 2 , wherein the driver controller circuit operates in a supply voltage domain and power switches in the PSH banks operate in a secondary voltage domain.
4. The droop reduction circuit of claim 2 ,
wherein the supply power rail is further coupled to a first load comprising a processing circuit, and the secondary power rail is further coupled to a second load comprising a memory cell array.
5. The droop reduction circuit of claim 2 , wherein the secondary voltage is supplied by a low-dropout (LDO) voltage regulator on the die.
6. The droop reduction circuit of claim 2 , wherein the secondary voltage is less than 1 volt.
7. The droop reduction circuit of claim 2 , wherein each PSH bank includes one or more thin-oxide metal oxide semiconductor field-effect transistor (MOSFET) switches.
8. The droop reduction circuit of claim 2 , wherein each PSH bank includes one or more power switches, and at least one PSH bank includes a different number of power switches from another PSH bank.
9. The droop reduction circuit of claim 2 , wherein the driver controller circuit outputs drive signals to turn on or off of the PSH banks independently of one another.
10. The droop reduction circuit of claim 2 , wherein, in response to the voltage droop, the driver controller circuit is operative to output N drive signals in parallel to turn on N PSH banks in parallel.
11. The droop reduction circuit of claim 2 , wherein the driver controller circuit is operative to output N drive signals sequentially with a delay between consecutive ones of the drive signals to stagger turning off N PSH banks.
12. A method of a droop reduction circuit on a die, comprising:
detecting voltage droop in a supply voltage received by a first load;
generating drive signals to turn on power switch (PSH) banks in response to detection of the voltage droop; and
pulling up the voltage droop by a plurality of power switches in the PSH banks, each power switch having an input terminal to receive a secondary voltage and a gate terminal to receive one of the drive signals, wherein the secondary voltage is higher than the supply voltage and is received by a second load on the die;
generating N drive signals sequentially with a delay between consecutive ones of the drive signals to stagger turning off N PSH banks; and
setting a length of the delay with a delay chain of M multiplexers controlled by a configurable M-bit one-hot code containing at most one non-zero bit.
13. The method of claim 12 ,
wherein the supply power rail is further coupled to the first load comprising a processing circuit, the secondary power rail is further coupled to the second load comprising a memory cell array.
14. The method of claim 12 , further comprising:
supplying the secondary voltage to the second load by a low-dropout (LDO) voltage regulator on the die.
15. The method of claim 12 , wherein each PSH bank includes one or more thin-oxide metal oxide semiconductor field-effect transistor (MOSFET) switches.
16. The method of claim 12 , further comprising:
generating the drive signals to turn on or off of the PSH banks independently of one another.
17. The method of claim 12 , further comprising:
in response to the voltage droop, generating N drive signals in parallel to turn on N PSH banks in parallel.