IP Library Granted Patent US 11,259,403
Granted Patent B1
US 11,259,403 · App. 17/085,749 · Granted Feb 22, 2022

Printed circuit board structure for solid state drives

Inventors: Wenwei Wang (San Jose, CA); Xiaofang Chen (Milpitas, CA); Danyang Qiao (Santa Clara, CA); Sonny Mirador (Milpitas, CA)
Assignee: SK hynix Inc.
H05K1/0236H05K1/0231H05K2201/093
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Quick Facts
Patent No.
US 11,259,403
App. No.
17/085,749
Granted
Feb 22, 2022
Kind
B1
Abstract

A printed circuit board (PCB) structure is provided for a solid state drive. In an embodiment, a solid state drive includes top and bottom layers, multiple intermediate layers and a ground cage. Each of top and bottom layers includes a plurality of components for operation of the solid state drive. The multiple intermediate layers enable electrical signals to pass between components on the top and bottom layers, one of the multiple intermediate layers including a power plane having a high voltage relative to each of the other planes. The ground cage shields signal traces on the same layer as the power plane and planes in adjacent layers from noise generated by the power plane.

Claims (20)

1. A printed circuit board for a solid state drive, comprising:

top and bottom layers, each of which includes a plurality of components for operation of the solid state drive; and

multiple intermediate layers disposed between the top and bottom layers and configured to enable electrical signals to pass between components on the top and bottom layers,

wherein the multiple intermediate layers include:

a first intermediate layer including a high power plane having a high voltage and first and second signal traces adjacent to the high power plane;

a second intermediate layer formed above the first intermediate layer and below the top layer and including a first low power plane having a low voltage less than the high voltage;

a third intermediate layer formed below the first intermediate layer and above the bottom layer and including a second low power plane having the low voltage; and

a ground cage configured to enclose the high power plane such that capacitive and inductive paths between the high power plane and each of the first and second signal traces and capacitive and inductive paths between the high power plane and each of the first and second low power planes are blocked.

2. The printed circuit board of claim 1 , wherein the ground cage includes:

a first ground plane disposed between the high power plane of the first immediate layer and the first lower power plane of the second immediate layer;

a second ground plane disposed between the high power plane of the first immediate layer and the second lower power plane of the third immediate layer;

a third ground plane disposed between the high power plane and the first signal trace of the first immediate layer; and

a fourth ground plane disposed between the high power plane and the second signal trace of the first immediate layer.

3. The printed circuit board of claim 2 , wherein the first to fourth ground planes are electrically coupled.

4. The printed circuit board of claim 3 , wherein each of the first and second ground planes is disposed such that there is a first gap between the first immediate layer and each of the second and third immediate layers.

5. The printed circuit board of claim 4 , wherein each of the third and fourth ground planes is disposed such that there is a second gap between the high power plane and each of the first and second signal traces, the second gap different from the first gap.

6. The printed circuit board of claim 5 , wherein each gap contains epoxy laminate material.

7. The printed circuit board of claim 5 , wherein each of the first and second ground planes has a first thickness.

8. The printed circuit board of claim 7 , wherein each of the high power plane, the first and second signal traces and the first and second ground planes has a second thickness different from the first thickness.

9. The printed circuit board of claim 1 , wherein each of the second and third intermediate layers further includes a signal trace.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2021
From: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
To: SK HYNIX INC.
Reel/Frame 056883/0151 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2020
From: WANG, WENWEI; CHEN, XIAOFANG; QIAO, DANYANG; MIRADOR, SONNY
To: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
Reel/Frame 054228/0014 →