Memory device

1. A memory device, comprising:

a first tier disposed on a substrate, wherein the first tier comprises:

a first layer stack, wherein the first stack layer comprises a first dielectric layer, a first conductive layer disposed on the first dielectric layer, a second dielectric layer disposed on the first conductive layer, and a second conductive layer disposed on the second dielectric layer;

a first gate electrode, penetrating through the first layer stack;

a first channel layer, disposed between the first layer stack and the first gate electrode, wherein the first channel layer is in contact with the first dielectric layer, the first conductive layer, the second dielectric layer and the second conductive layer; and

a first ferroelectric layer, disposed between the first channel layer and the first gate electrode; and

a second tier disposed on the first tier, wherein the second tier comprises:

a second layer stack;

a second gate electrode, penetrating through the second layer stack;

a second channel layer, disposed between the second layer stack and the second gate electrode; and

a second ferroelectric layer, disposed between the second channel layer and the second gate electrode, wherein the second gate electrode is disposed above the first gate electrode, and the first and second gate electrodes are electrically independent to each other.

2. The memory device of claim 1 , wherein the first dielectric layer and the first conductive layer have a first width, the second dielectric layer and the second conductive layer have a second width, and the second width is less than the first width.

3. The memory device of claim 1 , wherein the second layer stack comprises:

a third conductive layer, disposed over the second conductive layer;

a third dielectric layer, disposed on the third conductive layer;

a fourth conductive layer, disposed on the third dielectric layer; and

a fourth dielectric layer, disposed on the fourth conductive layer, wherein the second channel layer is in contact with the third conductive layer, the third dielectric layer, the fourth conductive layer, and the fourth dielectric layer.

4. The memory device of claim 3 , wherein the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is greater than the third width.

5. The memory device of claim 3 , wherein the first and fourth conductive layers are connected to a first connector positioned between the first tier and the second tier, and the second and third conductive layers are connected to a second connector positioned between the first tier and the second tier which is different from the first connector.

6. The memory device of claim 1 , wherein the first gate electrode is connected to a third connector, the second gate electrode is connected to a fourth connector, and the third and fourth connectors are electrically independent to each other.

7. The memory device of claim 1 , wherein the first ferroelectric layer laterally wraps the first gate electrode, and the second ferroelectric layer laterally wraps the second gate electrode.

8. The memory device of claim 1 , further comprising a dielectric material vertically disposed between the first tier and the second tier.

9. The memory device of claim 1 , further comprising an additional tier disposed on the second tier, wherein the additional tier comprises an additional layer stack; an additional gate electrode penetrating through the additional layer stack; an additional channel layer disposed between the additional layer stack and the additional gate electrode; and an additional ferroelectric layer disposed between the additional channel layer and the additional gate electrode.

10. A memory device, comprising:

a first layer stack disposed on a substrate, wherein the first layer stack comprises a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second S/D layer stacked in order;

a first conductive pillar, penetrating through the first layer stack;

a first ferroelectric layer, wrapping the first conductive pillar;

a first channel layer, disposed between the first layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar; wherein the first channel layer is in contact with the first dielectric layer, the first source/drain (S/D) layer, the second dielectric layer, and the second S/D layer; and

a second layer stack disposed on the first layer stack, wherein the second layer stack comprises a third S/D layer, a third dielectric layer, a fourth S/D layer, and a fourth dielectric layer stacked in order, wherein the first S/D layer is electrically coupled to the fourth S/D layer through a first connector positioned between the first layer stack and the second layer stack, while the second S/D layer is electrically coupled to the third S/D layer through a second connector positioned between the first layer stack and the second layer stack, wherein the first connector and the second connector are electrically isolated from each other by an insulation layer positioned between the first layer stack and the second layer stack.

11. The memory device of claim 10 , wherein a portion of the first S/D layer is exposed by the second dielectric layer and the second S/D layer to form a staircase shaped region.

12. The memory device of claim 11 , further comprising:

a first contact plug, disposed on the first S/D layer in the staircase shaped region;

a second contact plug, disposed on the second S/D layer in the staircase shaped region, wherein the first contact plug has a length greater than a length of the second contact plug;

a second conductive pillar, disposed above the first conductive pillar and penetrating through the second layer stack;

a second ferroelectric layer, wrapping the second conductive pillar; and

a second channel layer, disposed between the second layer stack and the second ferroelectric layer, wherein the second ferroelectric layer is in contact with the second channel layer and the second conductive pillar, and the first and second conductive pillars are electrically independent to each other.

13. The memory device of claim 10 , wherein a material of the first channel layer comprises indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tungsten oxide (IWO), tungsten oxide (WO), tantalum oxide (TaO), molybdenum oxide (MoO), or a combination thereof.

14. The memory device of claim 10 , wherein a material of the first ferroelectric layer comprises HZO, HSO, HfSiO, HfLaO, HfO 2 , HfZrO 2 , ZrO 2 , or HfO 2 doped by La, Y, Si, or Ge.