Apparatuses, methods, and systems for hashing instructions
Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.
1. A processor comprising:
a decode circuit to decode a single instruction into a decoded single instruction, the single instruction comprising at least one first field that identifies eight 64-bit state elements A, B, C, D, E, F, G, and H for a round according to a SHA512 hashing standard and at least one second field that identifies an input message; and
an execution circuit to execute the decoded single instruction to:
perform a first bitwise XOR operation on the state element A rotated right by 28 bits, the state element A rotated right by 34 bits, and the state element A rotated right by 39 bits to form a first value,
perform a second bitwise XOR operation on the state element E rotated right by 14 bits, the state element E rotated right by 18 bits, and the state element E rotated right by 41 bits to form a second value,
perform two rounds according to the SHA512 hashing standard on the input message, first value, second value, state element A, state element B, state element C, state element D, state element E, state element F, state element G, and state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and
store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.
2. The processor of claim 1 , wherein the at least one first field includes:
a first register field that identifies a first register that stores state elements C, D, G, and H, and
a second register field that identifies a second register that stores state elements A, B, E, and F.
3. The processor of claim 2 , wherein the at least one second field includes a third register field that identifies the input message.
4. The processor of claim 3 , wherein the input message is two 64-bit message elements.
5. The processor of claim 2 , wherein the location specified by the single instruction to store the updated state element A, the updated state element B, the updated state element E, and the updated state element F is the first register.
6. The processor of claim 1 , wherein:
the decode circuit is to decode a second instruction into a decoded second instruction, the second instruction comprising at least one field that identifies five 64-bit input message elements according to the SHA512 hashing standard; and
the execution circuit is to execute the decoded second instruction to:
generate the input message based on the five 64-bit input message elements, and
store the input message in a location specified by the at least one field of the second instruction.
7. The processor of claim 6 , wherein the input message generated by the second instruction comprises a plurality of 64-bit message elements.
8. The processor of claim 1 , wherein:
the decode circuit is to decode a second instruction into a decoded second instruction, the second instruction comprising at least one field that identifies six 64-bit input message elements including four intermediate message elements from an intermediate calculation for a round according to the SHA512 hashing standard; and
the execution circuit is to execute the decoded second instruction to:
determine a plurality of 64-bit final message elements based on the six 64-bit input message elements, and
store the plurality of 64-bit final message elements in a location specified by the at least one field of the second instruction.
9. A method comprising:
decoding a single instruction by a decode circuit of a processor into a decoded single instruction, the single instruction comprising at least one first field that identifies eight 64-bit state elements A, B, C, D, E, F, G, and H for a round according to a SHA512 hashing standard and at least one second field that identifies an input message; and
executing the decoded single instruction by an execution circuit of the processor to:
perform a first bitwise XOR operation on the state element A rotated right by 28 bits, the state element A rotated right by 34 bits, and the state element A rotated right by 39 bits to form a first value,
perform a second bitwise XOR operation on the state element E rotated right by 14 bits, the state element E rotated right by 18 bits, and the state element E rotated right by 41 bits to form a second value,
perform two rounds according to the SHA512 hashing standard on the input message, first value, second value, state element A, state element B, state element C, state element D, state element E, state element F, state element G, and state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and
store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.
10. The method of claim 9 , wherein the at least one first field includes:
a first register field that identifies a first register that stores state elements C, D, G, and H, and
a second register field that identifies a second register that stores state elements A, B, E, and F.
11. The method of claim 10 , wherein the at least one second field includes a third register field that identifies the input message.
12. The method of claim 11 , wherein the input message is two 64-bit message elements.
13. The method of claim 10 , wherein the location specified by the single instruction to store the updated state element A, the updated state element B, the updated state element E, and the updated state element F is the first register.
14. The method of claim 9 , further comprising:
decoding a second instruction by the decoder circuit into a decoded second instruction, the second instruction comprising at least one field that identifies five 64-bit input message elements according to the SHA512 hashing standard; and
executing the decoded second instruction by the execution circuit to:
generate the input message based on the five 64-bit input message elements, and
store the input message in a location specified by the at least one field of the second instruction.
15. The method of claim 14 , wherein the input message generated by the second instruction comprises a plurality of 64-bit message elements.
16. The method of claim 9 , wherein:
decoding a second instruction by the decoder circuit into a decoded second instruction, the second instruction comprising at least one field that identifies six 64-bit input message elements including four intermediate message elements from an intermediate calculation for a round according to the SHA512 hashing standard; and
executing the decoded second instruction by the execution circuit to:
determine a plurality of 64-bit final message elements based on the six 64-bit input message elements, and
store the plurality of 64-bit final message elements in a location specified by the at least one field of the second instruction.
17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction by a decode circuit of a processor into a decoded single instruction, the single instruction comprising at least one first field that identifies eight 64-bit state elements A, B, C, D, E, F, G, and H for a round according to a SHA512 hashing standard and at least one second field that identifies an input message; and
executing the decoded single instruction by an execution circuit of the processor to:
perform a first bitwise XOR operation on the state element A rotated right by 28 bits, the state element A rotated right by 34 bits, and the state element A rotated right by 39 bits to form a first value,
perform a second bitwise XOR operation on the state element E rotated right by 14 bits, the state element E rotated right by 18 bits, and the state element E rotated right by 41 bits to form a second value,
perform two rounds according to the SHA512 hashing standard on the input message, first value, second value, state element A, state element B, state element C, state element D, state element E, state element F, state element G, and state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and
store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.
18. The non-transitory machine readable medium of claim 17 , wherein the at least one first field includes:
a first register field that identifies a first register that stores state elements C, D, G, and H, and
a second register field that identifies a second register that stores state elements A, B, E, and F.
19. The non-transitory machine readable medium of claim 18 , wherein the at least one second field includes a third register field that identifies the input message.
20. The non-transitory machine readable medium of claim 19 , wherein the input message is two 64-bit message elements.
21. The non-transitory machine readable medium of claim 18 , wherein the location specified by the single instruction to store the updated state element A, the updated state element B, the updated state element E, and the updated state element F is the first register.
22. The non-transitory machine readable medium of claim 17 , further comprising:
decoding a second instruction by the decoder circuit into a decoded second instruction, the second instruction comprising at least one field that identifies five 64-bit input message elements according to the SHA512 hashing standard; and
executing the decoded second instruction by the execution circuit to:
generate the input message based on the five 64-bit input message elements, and
store the input message in a location specified by the at least one field of the second instruction.
23. The non-transitory machine readable medium of claim 22 , wherein the input message generated by the second instruction comprises a plurality of 64-bit message elements.
24. The non-transitory machine readable medium of claim 17 , wherein:
decoding a second instruction by the decoder circuit into a decoded second instruction, the second instruction comprising at least one field that identifies six 64-bit input message elements including four intermediate message elements from an intermediate calculation for a round according to the SHA512 hashing standard; and
executing the decoded second instruction by the execution circuit to:
determine a plurality of 64-bit final message elements based on the six 64-bit input message elements, and
store the plurality of 64-bit final message elements in a location specified by the at least one field of the second instruction.