Configurable scheduler with pre-fetch and invalidate threads in a graph stream processing system

1. A graph stream processing system, comprising:

a plurality of graph streaming processors operative to process a plurality of main threads and a plurality of prefetch threads, wherein each of the plurality of main threads include a set of instructions operating on the plurality of graph streaming processors and operating on a set of input data and producing output data; and

a scheduler comprising plurality of stages, wherein each stage of the plurality of stages is coupled to an input command buffer and an output command buffer,

wherein the each stage includes physical hardware implemented using digital logic gates, operative to schedule each of the plurality of prefetch threads and each of the plurality of main threads, the each stage comprising of a command parser, a main thread generator, a prefetch thread generator, and a thread scheduler,

wherein the command parser operative to interpret commands within a corresponding input command buffer,

wherein the main thread generator and the prefetch thread generator are coupled to the command parser operative to generate the plurality of main threads and the plurality of prefetch threads respectively,

wherein the thread scheduler, coupled to the prefetch thread generator dispatches the plurality of prefetch threads operative to prefetch instructions from memory into a data buffer;

wherein the thread scheduler, coupled to the main thread generator dispatches the plurality of main threads for operating on the plurality of graph streaming processors, with one or more main threads running one or more code blocks on different input data and producing different output data.

2. The system of claim 1 , wherein the thread scheduler dispatches the plurality of prefetch threads before dispatching at least one of the plurality of main threads of the each stage.

3. The system of claim 1 , further comprising an invalidate thread generator, wherein the invalidate thread generator is coupled to the command parser operative to generate a plurality of invalidate threads.

4. The system of claim 3 , further wherein the plurality of invalidate threads operate to invalidate at least a location in the data buffer.

5. The system of claim 3 , where in the thread scheduler dispatches the plurality of invalidate threads after execution of the plurality of main threads of the each stage.

6. The system of claim 3 , wherein the plurality of graph streaming processors operate simultaneously on the plurality of prefetch threads, the plurality of main threads and the plurality of invalidate threads of different stages.

7. The system of claim 3 , wherein the plurality of graph streaming processors operate simultaneously on the plurality of main threads of a stage of the plurality of stages and the plurality of prefetch threads of a next stage of the plurality of stages and the plurality of invalidate threads of a previous stage of the plurality of stages.

8. The system of claim 3 , wherein the plurality of graph streaming processors operate simultaneously on the plurality of main threads of a stage of the plurality of stages and the plurality of prefetch threads of the stage or operate simultaneously on the plurality of main threads of the stage and the plurality of invalidate threads of the stage.

9. The system of claim 1 , wherein the plurality of graph streaming processors complete execution of at least one main thread of a first stage of the plurality of stages before the thread scheduler can dispatch at least one main thread from a second stage of the plurality of stages for operation on the plurality of graph streaming processors.

10. The system of claim 9 , wherein the commands to generate the plurality of main threads for the second stage is computed by the plurality of graph streaming processors operating on the at least one of main threads of the first stage.

11. The system of claim 1 , the graph streaming processor system further comprising a compiler to generate the one or more code blocks for operating on the plurality of graph streaming processors.

12. The system of claim 11 , the compiler provides input commands to initiate processing of the graph streaming processor system.

13. A method of graph stream processing, comprising:

processing, by a plurality of graph streaming processors, a plurality of main threads, wherein each of the plurality of main threads includes a set of instructions operating on a set of data and producing output data,

processing, by the plurality of graph streaming processors, a plurality of prefetch threads, wherein each of the plurality of prefetch threads includes a set of instructions operating to fetch data from memory and store in an on-chip memory,

scheduling the plurality of main threads and the plurality of prefetch threads by a scheduler,

wherein the scheduler includes a plurality of stages and a plurality of command buffers located between each stage of the plurality of stages, wherein the each stage includes physical hardware operative to schedule each of the plurality of prefetch threads and each of the plurality of main threads,

further comprising:

interpreting by the scheduler, commands within a corresponding input command buffer;

dispatching by the scheduler, one or more of the plurality of the prefetch threads where in each of the plurality of the prefetch threads operating to fetch data from memory and store in the on-chip memory,

dispatching by the scheduler, one or more of the plurality of the main threads for operating on the plurality of graph streaming processors, wherein each of the plurality of main threads operate on one or more code blocks but on different input data and producing different output data.

14. The method of claim 13 , further comprising an invalidate thread generator coupled to the command parser operative to generate a plurality of invalidation threads.

15. The method of claim 14 , further comprising dispatching by the thread scheduler, the invalidation thread after execution of the plurality of the main threads, operable to invalidate memory locations in the on-chip memory.

16. The method of claim 13 , further comprising executing the plurality of prefetch threads before dispatching the one or more main threads of the each stage.

17. The method of claim 14 , wherein the plurality of graph streaming processors executes at least one of the plurality of main threads of a first stage before the thread scheduler dispatches the plurality of invalidate threads of the each stage.

18. The method of claim 14 , further comprising dispatching simultaneously by the scheduler, the plurality of main threads of the each stage and the plurality of prefetch threads of the each stage or scheduling by the scheduler the plurality of main threads of the stage and the plurality of invalidate threads of the each stage.

19. The method of claim 14 , further comprising dispatching simultaneously by the scheduler, the plurality of main threads of the each stage, the plurality of prefetch threads of a next stage of the each stage and the plurality of invalidate threads of a previous stage of the each stage.

20. The method of claim 13 , wherein the plurality of graph streaming processors execute at least one of the plurality of main threads of a first stage of the each stage before the thread scheduler dispatches at least one of the plurality of main threads from a second stage of the each stage for execution.