Spacers for semiconductor devices including a backside power rails
Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
1. A device comprising:
a first transistor structure;
a front-side interconnect structure on a front-side of the first transistor structure; and
a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure comprising:
a first dielectric layer on the backside of the first transistor structure;
a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure;
a first conductive line electrically coupled to the first via; and
an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer; and
a second dielectric layer adjacent the first conductive line, the second dielectric layer defining a first horizontal boundary of the air spacer perpendicular to the first side boundary of the air spacer.
2. The device of claim 1 , wherein the first conductive line is a power line or an electrical ground line.
3. The device of claim 1 , further comprising:
a second via extending through the first dielectric layer, the second via being electrically coupled to a second source/drain region of the first transistor structure; and
a second conductive line electrically coupled to the second via, wherein the second conductive line defines a second side boundary of the air spacer opposite the first side boundary of the air spacer.
4. The device of claim 3 , further comprising:
a first spacer contacting the first conductive line; and
a second spacer contacting the second conductive line, wherein the first spacer defines a third side boundary of the air spacer, and wherein the second spacer defines a fourth side boundary of the air spacer opposite the third side boundary.
5. The device of claim 4 , wherein an aspect ratio of a height of the air spacer to a width of the air spacer between the first spacer and the second spacer is from 1 to 2.
6. The device of claim 1 , wherein the first dielectric layer defines a second horizontal boundary of the air spacer.
7. The device of claim 1 , wherein a horizontal surface of the second dielectric layer is level with a horizontal surface of the first conductive line.
8. A device comprising:
a transistor structure;
a front-side interconnect structure on a front-side of the transistor structure; and
a backside interconnect structure on a backside of the transistor structure, the backside interconnect structure comprising:
a first conductive line electrically coupled to a first source/drain region of the transistor structure by a first backside via;
a first dielectric spacer contacting a side surface of the first conductive line; and
an air gap adjacent the first dielectric spacer, wherein a side surface of the first dielectric spacer defines a first boundary of the air gap and a side surface of the first conductive line defines a second boundary of the air gap.
9. The device of claim 8 , wherein a horizontal surface of the first dielectric spacer defines a third boundary of the air gap perpendicular to the first boundary and the second boundary.
10. The device of claim 9 , further comprising a first dielectric layer contacting a side surface of the first dielectric spacer, wherein a horizontal surface of the first dielectric layer defines a fourth boundary of the air gap perpendicular to the first boundary and the second boundary.
11. The device of claim 10 , wherein a horizontal surface of the first conductive line, a horizontal surface of the first dielectric spacer, and a horizontal surface of the first dielectric layer are level with one another.
12. The device of claim 10 , wherein an aspect ratio of a combined height of the first boundary and the second boundary to a width of the fourth boundary is from 1 to 2.
13. The device of claim 8 , wherein the first conductive line is a power line or an electrical ground line.
14. The device of claim 8 , wherein the air gap extends along three or more side surfaces of the first dielectric spacer and three or more side surfaces of the first conductive line in cross-sectional views.
15. A method comprising:
forming a first transistor on a first substrate;
exposing a first epitaxial material, wherein exposing the first epitaxial material comprises thinning a backside of the first substrate;
replacing the first epitaxial material with a first backside via, the first backside via being electrically coupled to a first source/drain region of the first transistor;
forming a first dielectric layer over the first backside via;
forming a first conductive line in the first dielectric layer over the first backside via, the first conductive line being electrically coupled to the first backside via;
forming a first spacer over the first dielectric layer adjacent the first conductive line;
removing the first dielectric layer to form a first recess exposing a sidewall of the first conductive line; and
sealing the first recess to form an air spacer.
16. The method of claim 15 , wherein forming the first spacer comprises:
depositing a second dielectric layer over the first dielectric layer and the first conductive line; and
etching the second dielectric layer to form the first spacer.
17. The method of claim 15 , further comprising etching back the first dielectric layer after forming the first conductive line and before forming the first spacer.
18. The method of claim 15 , wherein a ratio of a height of the first conductive line to a width of the air spacer adjacent the first spacer is from 1 to 3.
19. The method of claim 15 , wherein sealing the first recess comprises:
depositing a seal material over the first spacer, the first conductive line, and the first recess; and
planarizing the seal material, the first spacer, and the first conductive line.
20. The method of claim 15 , wherein exposing the first epitaxial material further exposes a second epitaxial material, wherein the method further comprises:
replacing the second epitaxial material with a second backside via, the second backside via being electrically coupled to a second source/drain region of the first transistor; and
forming a second conductive line over the second backside via, the second conductive line being electrically coupled to the second backside via, wherein removing the first dielectric layer to form the first recess exposes a sidewall of the second conductive line.