Memory system, memory controller, and operation method of memory system
Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.
1. A memory system comprising:
a memory device including memory cells to store data and operable to perform an operation on one or more memory cells including, a read operation for reading data stored in one or more memory cells, a program operation for writing new data into one or more memory cells, or an erase operation for deleting stored data in one or more memory cells; and
a memory controller in communication with the memory device and configured to control the memory device to perform an operation,
wherein the memory controller is configured to:
suspend a target operation that is being executed by the memory device based on i) whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and ii) a number of times the target operation is suspended, and
wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation.
2. The memory system of claim 1 , wherein the memory controller is configured to suspend the target operation upon a determination that the first operation is not executed, and that the suspension count of the target operation is less than a first reference number of suspensions.
3. The memory system of claim 2 , wherein the memory controller is configured to, when suspending the target operation after the target operation is resumed from a previous suspension, suspend the target operation only after a predetermined minimum delay time has passed since the resumption of the target operation.
4. The memory system of claim 3 , the memory controller is configured to determine the predetermined minimum delay time depending on whether the suspension count of the target operation is greater than or equal to a second reference number of suspensions when the target operation is an erase operation.
5. The memory system of claim 1 , wherein the memory controller is configured to resume the target operation based on whether the first operation is performed, and based on a number of the read operation executed after the target operation is suspended.
6. The memory system of claim 5 , wherein the memory controller is configured to resume the suspended target operation upon a determination that the first operation is executed, or that the number of the read operation executed after the target operation is suspended is greater than or equal to a first number of read operations.
7. The memory system of claim 6 , wherein the memory controller is configured to resume the suspended target operation upon a determination that the target operation is an erase operation, and that the number of the read operation executed after the target operation is suspended is greater than or equal to a second number of read operations.
8. The memory system of claim 7 , wherein the memory controller is configured to update the second number of read operations depending on whether a total number of the read operation executed while the target operation is in progress is greater than or equal to a third number of reads.
9. The memory system of claim 8 , wherein the third number of read operations is proportional to the suspension count of the target operation, and a reference number of read operations per suspended operation.
10. A memory controller comprising:
a memory interface configured to communicate with a memory device; and
a processor configured to communicate with the memory device through the memory interface to suspend the target operation based on whether a first operation configured to reset a reference read bias is performed upon occurrence of a failure in a read operation executed after the target operation is suspended, and based on a suspension count of the target operation,
wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation.
11. The memory controller of claim 10 , wherein the processor is configured to suspend the target operation upon a determination that the first operation is not executed, and that the suspension count of the target operation is less than a first reference number of suspensions.
12. The memory controller of claim 11 , wherein the processor is configured to, when suspending the target operation after the target operation is resumed from a previous suspension, suspend the target operation only after a predetermined minimum delay time has passed since the resumption of the target operation.
13. The memory controller of claim 12 , wherein the processor is configured to determine the predetermined minimum delay time depending on whether the suspension count of the target operation is greater than or equal to a second reference number of suspensions when the target operation is an erase operation.
14. The memory controller of claim 10 , wherein the processor is configured to resume the target operation based on whether the first operation is performed, and based on a number of the read operation executed after the target operation is suspended.
15. The memory controller of claim 14 , wherein the processor is configured to resume the suspended target operation upon a determination that the first operation is executed, or that the number of the read operation executed after the target operation is suspended is greater than or equal to a first number of read operations.
16. The memory controller of claim 15 , wherein the processor is configured to resume the suspended target operation upon a determination that the target operation is an erase operation, and that the number of the read operation executed after the target operation is suspended is greater than or equal to a second number of read operations.
17. The memory controller of claim 16 , wherein the processor is configured to update the second number of read operations depending on whether a total number of the read operation executed while the target operation is in progress is greater than or equal to a third number of reads.
18. The memory controller of claim 17 , wherein the third number of read operations is proportional to the suspension count of the target operation, and a reference number of read operations per suspended operation.
19. An operation method of a memory system, the method comprising:
determining, while a target operation is in progress, whether a first operation configured to reset a reference read bias is performed upon occurrence of a failure in a read operation executed after the target operation is suspended, and based on a suspension count of the target operation; and
suspending the target operation based on whether the first operation is performed and the suspension count of the target operation,
wherein the target operation includes a program operation or an erase operation that has been in progress when suspending the target operation.
20. The operation method of claim 19 , further comprising resuming the target operation based on whether the first operation is performed and based on a number of the read operation executed after the target operation is suspended.