IP Library Granted Patent US 11,508,273
Granted Patent B2
US 11,508,273 · App. 17/096,726 · Granted Nov 22, 2022

Built-in test of a display driver

Inventors: Masao Orio (Tokyo, JP); Takashi Nose (Kanagawa, JP); Hirobumi Furihata (Tokyo, JP); Akio Sugiyama (Tokyo, JP); Kota Kitamura (Tokyo, JP); Chirinjeev Singh (San Jose, CA); Dipankar Talukdar (San Jose, CA); Guozhong Shen (Fremont, CA)
Assignee: Synaptics Incorporated
G09G3/006G09G2320/0673G09G2330/12
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Quick Facts
Patent No.
US 11,508,273
App. No.
17/096,726
Granted
Nov 22, 2022
Kind
B2
Abstract

A display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and generate second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

Claims (71)

1. A display driver, comprising:

image processing circuitry configured to:

generate first output data during a first display update period, and

generate second output data during a second display update period, wherein the

image processing circuitry comprises:

storage circuitry, and

a first image processing component configured to:

generate intermediate data used to generate the first output data during the first display update period,

store the intermediate data in the storage circuitry before a test period,

acquire the intermediate data from the storage circuitry after the test period, and

use the intermediate data to generate the second output data during the second display update period,

driver circuitry configured to:

update a display panel based on the first output data during the first display update period, and

update the display panel based on the second output data during the second display update period; and

test circuitry configured to test the image processing circuitry during the test period disposed between the first display update period and the second display update period.

2. The display driver of claim 1 , wherein the image processing circuitry comprises a plurality of image processing components,

wherein the image processing circuitry is configured to bypass the first image processing component of the plurality of image processing components to generate third output data in response to the test circuitry detecting a failure of the first image processing component.

3. The display driver of claim 1 , wherein the first image processing component is configured used to generate the first output data and the second output data, and

wherein the image processing circuitry further comprises:

a second image processing component configured to generate third output data in place of the first image processing component in response to the test circuitry detecting a failure of the first image processing component, and

wherein the driver circuitry is further configured to update the display panel based on the third output data.

4. The display driver of claim 3 , wherein the first image processing component and the second image processing component are both configured to perform a gamma transformation.

5. A display driver comprising:

image processing circuitry configured to:

generate first output data during a first display update period, and

generate second output data during a second display update period,

wherein the image processing circuitry comprises:

a scan chain comprising a scan flipflop;

a data save flipflop configured to:

receive and store first data from the scan flipflop, and

restore the first data to the scan flipflop,

driver circuitry configured to:

update a display panel based on the first output data during the first display update period, and

update the display panel based on the second output data during the second display update period; and

test circuitry configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

6. The display driver of claim 5 , wherein the data save flipflop is configured to:

receive the first data from the scan flipflop at an end of the first display update period; and

restore the first data to the scan flipflop after testing the image processing circuitry.

7. The display driver claim 1 ,

wherein the image processing circuitry comprises a plurality of pixel pipes configured to perform a same image processing on a same test data in parallel, and

wherein testing the image processing circuitry is based on comparison of outputs from the plurality of pixel pipes.

8. The display driver of claim 7 , wherein the image processing circuitry is further configured to deliver the same test data to the plurality of pixel pipes in the testing of the image processing circuitry.

9. The display driver of claim 8 , wherein testing the image processing circuitry comprises detecting a failure of the image processing circuitry in response to one of the outputs from the plurality of pixel pipes being different from a remaining one or more of the outputs from the plurality of pixel pipes.

10. The display driver of claim 8 , wherein the test circuitry is further configured to generate the test data.

11. The display driver of claim 1 , further comprising:

proximity sensing circuitry configured to:

acquire a resulting signal from a sensor element disposed in a sensing region during a proximity sensing period that at least partially overlaps the test period; and

detect an input object in the sensing region based on the resulting signal.

12. The display driver of claim 1 , wherein the test circuitry is configured to notify a host of a detection of a failure of the image processing circuitry, the host being external to the display driver.

13. A display system, comprising:

a display panel; and

a display driver comprising:

image processing circuitry configured to:

generate first output data during a first display update period, and

generate second output data during a second display update period,

wherein the image processing circuitry comprises:

a scan chain comprising a scan flipflop, and

a data save flipflop configured to:

 receive and store first data from the scan flipflop, and

 restore the first data to the scan flipflop,

driver circuitry configured to:

update the display panel based on the first output data during the first display update period, and

update the display panel based on the second output data during the second display update period; and

test circuitry configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

14. The display system of claim 13 , wherein the image processing circuitry comprises a plurality of pixel pipes configured to perform same image processing in parallel,

wherein testing the image processing circuitry is based on comparison of outputs from the plurality of pixel pipes.

15. The display system of claim 13 , further comprising a host external to the display driver,

wherein the test circuitry is configured to generate a failure notification to notify the host of a detection of a failure of the image processing circuitry.

16. The display system of claim 15 , wherein the host is configured to output an alert indicating the detection of the failure from an output device in response to the failure notification.

17. The display system of claim 16 , wherein the host is configured to supply image data corresponding to an alert image to the display driver in response to the failure notification, and

wherein the display driver is configured to display the alert image.

Assignments (2)
SECURITY INTEREST Recorded Mar 12, 2021
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 055581/0737 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2020
From: ORIO, MASAO; NOSE, TAKASHI; FURIHATA, HIROBUMI; SUGIYAMA, AKIO; KITAMURA, KOTA; SINGH, CHIRINJEEV; TALUKDAR, DIPANKAR; SHEN, GUOZHONG
To: SYNAPTICS INCORPORATED
Reel/Frame 054436/0380 →