Method and circuit for protecting a DRAM memory device from the row hammer effect

1. A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one prevention logic configured to respectively define sub-banks dividing each bank as contiguous sections of rows, the prevention logic being configured to execute, at each activation of a row of a given sub-bank, a step of incrementing an activation counter associated with the given sub-bank and being configured to execute a preventive refresh sequence comprising:

a step of identifying a need for preventive refresh of a determined sub-bank of the sub-banks of the memory device;

a step of triggering an operation to refresh a current row designated by a current row index associated with the determined sub-bank;

a step of incrementing the current row index associated with the determined sub-bank;

wherein the preventive refresh sequence is forming a percentage of progress of a preventive refresh cycle, the preventive refresh cycle leading to refresh at least all the rows of the determined sub-bank, and wherein the preventive refresh cycle of the determined sub-bank is entirely executed before the number of rows activated in the determined sub-bank exceed a critical hammer value.

2. The protection method according to claim 1 wherein each sub-bank is associated with an activation threshold, and the prevention logic is configured to determine a required number of preventive refreshes of the given sub-bank.

3. The protection method according to claim 2 , in which the determination of the required number of preventive refreshes comprises the incrementing of a pending refresh counter, the preventive refresh sequence comprises a step of decrementing the pending counter refresh, and the preventive refresh sequence is executed repeatedly as long as the pending refresh counter exceeds a floor value.

4. The protection method according to claim 2 , in which an index of a given sub-bank is inserted into a list of sub-banks awaiting refresh when the required number of preventive refreshes of the given sub-bank reaches the value 1.

5. The protection method according to claim 4 , in which the list is formed by chaining between them entries of a data structure.

6. The protection method according to claim 4 , in which the step of identifying a need for preventive refresh of the determined sub-bank consists in identifying that the list of sub-banks awaiting refresh is not empty.

7. The protection method according to claim 4 , in which the index of a given sub-bank is removed from the list when the required number of preventive refreshes of the given sub-bank goes under the value 1.

8. The protection method according to claim 2 , in which the step of identifying a need for preventive refresh of the determined sub-bank is executed at the end of the step of incrementing the activation counter of a given sub-bank, and comprises a comparison of the required number of preventive refresh of the given sub-bank with a determined threshold.

9. The protection method according to claim 2 , in which the determination of a required number of preventive refreshes comprises:

a step of incrementing, in a modulo operation, the activation threshold, the activation counter of the given sub-bank;

incrementation of the required number of preventive refreshes of the given sub-bank, if the step of incrementing the activation threshold has reset the activation counter of the given sub-bank to zero.

10. The protection method according to claim 9 , in which the activation counter is incremented by a parameter strictly less than the activation threshold.

11. The protection method according to claim 2 wherein at each activation of a row of a given sub-bank of the memory device, the step of incrementing the activation counter associated with the given sub-bank also increments the activations counters of all other sub-banks having at least a row likely to be hammered by the activation.

12. The protection method according to claim 2 , in which the activation threshold of a sub-bank is variable with temperature, supply voltage, frequency of the activations of a sub-bank, or the memory characteristics.

13. The protection method according to claim 2 , in which the activation threshold is distinct from one sub-bank to another.

14. The protection method according to claim 1 , wherein the triggering of an operation to refresh a current row comprises its storage in a buffer memory.

15. The protection method according to claim 1 , in which the preventive refresh cycle also leads to refresh at least twice the rows of a low internal margin and of a high internal margin of the determined sub-bank.

16. The protection method according to claim 1 , in which the step of triggering an operation to refresh a current row comprises the insertion of a preventive refresh request in a control traffic intended for the memory bank in which the determined sub-bank resides.

17. The protection method according to claim 1 , wherein a bank is decomposed into sub-banks of different sizes.

18. The protection method according to claim 1 , in which the prevention logic is associated with a plurality of banks.

19. The protection method according to claim 1 , wherein each sub-bank is associated with an activation threshold, and the prevention logic is configured to periodically execute a step of incrementing an activation counter associated with each sub-bank and to determine a required number of preventive refreshes of the sub-banks.

20. A DRAM memory device, buffer circuit or controller of a DRAM memory device comprising row hammer effect prevention logic configured to implement a protection method according to one of claim 1 .

21. A DRAM memory device according to claim 20 in which the DRAM memory device comprises at least one integrated processor.

22. A DRAM memory device according to the claim 20 , wherein the DRAM memory device comprises a plurality of replacement blocks, the replacement blocks being separated from each other by any means preventing a row of a replacement block from attacking by hammer a row of another replacement block.

23. A DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 22 in which the rows of a replacement block are intended to replace defective rows of a single sub-bank.

24. A DRAM memory device according to claim 22 in which the rows of a replacement block are intended to replace defective rows of a plurality of sub-banks, the rows composing the replacement block being all part of the preventive refresh cycle of the sub-banks sharing the replacement block.

25. DRAM memory device, buffer circuit or controller of a DRAM memory device according to the claim 22 , wherein a replacement block is defining a sub-bank.

26. DRAM memory device, buffer circuit or controller of a DRAM memory device according to claim 20 , in which the DRAM sub-banks comprise replacement rows, these replacement rows being part of the preventive refresh cycle of the sub-banks.

27. A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one prevention logic configured to respectively define sub-banks as contiguous sections of rows of a bank, the prevention logic being configured to execute a preventive refresh sequence comprising:

a step of identifying a need for preventive refresh of a determined sub-bank of the sub-banks of the memory device;

a step of triggering an operation to refresh a current row designated by a current row index associated with the determined sub-bank;

a step of incrementing the current row index associated with the determined sub-bank;

wherein the preventive refresh sequence is forming a step of a preventive refresh cycle leading to refresh at least all the rows of the determined sub-bank, and wherein the preventive refresh cycle of the determined sub-bank is entirely executed before the number of rows activated in the determined sub-bank exceed a critical hammer value,

wherein each sub-bank is associated with an activation threshold, and the prevention logic is configured to execute, at each activation of a row of a given sub-bank of the sub-banks of the memory device, a step of incrementing an activation counter associated with the given sub-bank and to determine a required number of preventive refreshes of the given sub-bank, and in which the required number of preventive refreshes of each given sub-bank is stored in a data structure.

28. The protection method according to claim 27 wherein the data structure is a tree like structure.

29. The protection method according to claim 27 , in which the step of identifying a need for preventive refresh of the determined sub-bank comprises browsing the data structure to identify a sub-bank whose required number of preventive refreshes is greater than or equal to 1.

30. The protection method according to claim 27 , in which the required number of preventive refreshes of all the sub-banks is less than 1, and the step of identifying a need for preventive refresh of the determined sub-bank comprises identification, in the data structure, of the sub-bank whose activation counter is maximum and resetting of the activation counter following the triggering of the operation to refresh.

31. A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one prevention logic configured to respectively define sub-banks as contiguous sections of rows of a bank, the prevention logic being configured to execute a preventive refresh sequence comprising:

a step of identifying a need from preventive refresh of a determined sub-bank of the sub-bank of the memory device;

a step of triggering an operation to refresh a current row designated by a current row index associated with the determined sub-bank;

a step of incrementing the current row index associated with the determined sub-bank;

wherein the preventive refresh sequence is forming a step of preventive refresh cycle leading to refresh at least all the rows of the determined sub-bank, and wherein the preventive refresh cycle of the determined sub-bank is entirely executed before the number of rows activated in the determined sub-bank exceed a critical hammer value,

wherein each sub-bank associated with an activation threshold, and the prevention logic is configured to execute, at each activation of a row of a given sub-bank of the sub-banks of the memory device, a step of incrementing an activation counter associated with the given sub-bank and to determine a required number of preventive refreshes of the given sub-banks, and in which the activation threshold defines a variable progress coefficient during a complete cycle of preventive refresh of the determined sub-bank.