System and method for providing granular processor performance control
A basic input/output system provides an interface for a core aggregation layout that identifies a grouping of processor cores into core aggregations, wherein each of the core aggregations is associated with a maximum allowable C-state. A processor may monitor an information handling system during operation of an application to gather data associated with latency sensitivity of the application, update the core aggregation layout based on the data gathered during the operation of the application, and pin a thread for execution to one of the processor cores based on the latency sensitivity of the application and the maximum allowable C-state.
1. A method comprising:
in response to determining that a current system configuration is not identical to a previous system configuration at a previous boot, grouping, by a processor, a plurality of processor cores into core aggregations, wherein each one of the core aggregations is associated with a maximum allowable C-state;
generating a map of the core aggregations based on the grouping to be used when routing a thread for execution; and
routing the thread for execution to one of the processor cores based on a latency requirement of the thread and the maximum allowable C-state of a core aggregation of the core aggregations as depicted in the map, wherein the routing the thread for the execution to the core aggregations is further based on a maximum size of an instruction set of the core aggregation.
2. The method of claim 1 , wherein the routing the thread for the execution to the core aggregation is further based on a minimum frequency of the core aggregation.
3. The method of claim 1 , wherein the each one of the core aggregations is further associated with a minimum frequency requirement of an application.
4. The method of claim 1 , wherein the each one of the core aggregations is further associated with the maximum size of an instruction set requirement of an application.
5. The method of claim 1 , wherein the each one of the core aggregations is further associated with a different minimum frequency and a different maximum size of the instruction set.
6. The method of claim 1 , wherein the thread is a latency-sensitive thread and the core aggregation has C-state disabled.
7. The method of claim 6 , further comprising generating a report associated with execution of the thread.
8. An information handling system, comprising:
a basic input/output system configured to provide an interface for a core aggregation layout that identifies a grouping of a plurality of processor cores into core aggregations, wherein each of the core aggregations is associated with a maximum allowable C-state; and
a processor configured to:
monitor the information handling system during operation of an application to gather data associated with latency sensitivity of the application;
updating the core aggregation layout based on the data gathered during the operation of the application; and
pin a thread for execution to one of the processor cores based on the latency sensitivity of the application, the maximum allowable C-state, and on a maximum size of an instruction set of the application.
9. The information handling system of claim 8 , wherein the processor is further configured to pin the thread based on a minimum frequency of the application.
10. The information handling system of claim 8 , wherein the each one of the core aggregations is further associated with a minimum frequency.
11. The information handling system of claim 8 , wherein the each one of the core aggregations is further associated with a different minimum frequency and a different maximum size of the instruction set.
12. A method comprising:
monitoring, by a processor, a workload during execution to collect data for determining a latency requirement of the workload;
training a machine learning model using the data during the execution of the workload to generate a core aggregation layout that includes one or more core aggregations, wherein each core aggregation includes one or more processor cores, and wherein each one of the core aggregations is associated with a maximum allowable C-state;
mapping each of the processor cores to one of the core aggregations;
routing a thread for execution to one of the processor cores based on a latency sensitivity of the thread and the maximum allowable C-state, wherein the routing the thread for the execution to the one of the core aggregations is further based on a maximum size of an instruction set; and
determining whether the workload is executing within the latency sensitivity of the thread and the maximum allowable C-state.
13. The method of claim 12 , wherein the routing the thread for the execution to the one of the core aggregations is further based on a minimum frequency.
14. The method of claim 12 , wherein the each one of the core aggregations is further associated with a minimum frequency of an application.
15. The method of claim 12 , wherein the each one of the core aggregations is further associated with a different minimum frequency and a different maximum size of the instruction set.
16. The method of claim 12 , wherein the thread is a latency-sensitive thread and the one processor core has C-state disabled.
17. The method of claim 12 , further comprising reporting the mapping of the processor cores to the core aggregations to an operating system.