Packet relaying apparatus and packet relaying method

1. A packet processing apparatus that connects a distributed station and a central station by a wired communication, the packet processing apparatus comprising:

a first gate that opens and closes output of a first packet in which low delay is requested as compared to a second packet in the wired communication, with respect to the wired communication for each of the time slots in a subframe;

a second gate that opens and closes output of the second packet with respect to the wired communication for each of the time slots in the subframe; and

a processor configured to:

learn, from a flow rate of the first packet, a cyclic pattern of the first packet for each of the time slots in the subframe in a predetermined cycle;

set, for each of the time slots as a gate state of each of the first gate and the second gate, a priority state in which the first packet is output with priority, a normal state in which the first packet or the second packet is alternatively output, or a mixed state in which the normal state and the priority state are present in a mixed manner, and set, as a gate state of a predetermined time slot associated with the cyclic pattern, the priority state or the mixed state;

monitor a flow rate of each of the first packet and the second packet in the predetermined time slot that is set in the mixed state;

determine, from a monitoring result obtained from the monitoring, whether an amount of output delay of the first packet at the time of outputting the first packet and the second packet in the predetermined time slot is within an allowable amount;

allocate, when the amount of output delay of the first packet is within the allowable amount, the first packet and the second packet to the predetermined time slot; and

control the setting so as to set the gate state at output timing of the first packet allocated in the predetermined time slot to the priority state and set the gate state at output timing of the second packet allocated in the predetermined time slot to the normal state.

2. The packet processing apparatus according to claim 1 , wherein the setting includes:

measuring a flow rate of the first packet in a designated time slot for each of the predetermined cycles;

discriminating,

when there is no flow rate of the first packet in the designated time slot, that the gate state of the designated time slot is the normal state,

when there is a flow rate of the first packet and when the flow rate of the first packet is greater than or equal to a predetermined threshold, that the gate state of the designated time slot is the priority state, and

when there is the flow rate of the first packet and the flow rate of the first packet is less than the predetermined threshold, that the gate state of the designated time slot is the mixed state; and

setting,

when it is discriminated that the gate state of the designated time slot is the priority state during the predetermined cycle, the gate state of the designated time slot to the priority state,

when it is discriminated that the gate state of the designated time slot is the mixed state during the predetermined cycle, the gate state of the designated time slot to the mixed state, or

when it is discriminated that the gate state of the designated time slot is continuously the normal state across the predetermined cycles, the gate state of the designated time slot to the normal state.

3. The packet processing apparatus according to claim 1 , wherein the setting includes:

measuring a flow rate of the first packet in a designated time slot for each of the predetermined cycles,

discriminating,

when there is no flow rate of the first packet in the designated time slot, that a gate state of the designated time slot is the normal state, and

when there is a flow rate of the first packet, that the gate state of the designated time slot is the priority state, and

setting,

when it is discriminated that the gate state of the designated time slot is continuously the normal state across the predetermined cycles, the gate state of the designated time slot to the normal state,

when it is discriminated that the gate state of the designated time slot is continuously priority state across the predetermined cycles, the gate state of the designated time slot to the priority state, or

when it is discriminated that the gate states of the designated time slots are different across the predetermined cycles, the gate state of the designated time slot to the mixed state.

4. The packet processing apparatus according to claim 1 , wherein the controlling includes:

copying, when the gate state of the predetermined time slot is the mixed state and when the amount of output delay of the first packet is within the allowable amount, the second packets in units of packets, outputting the second packets from the second gate, and deleting the copied second packets after the completion of the output of the second packets, and

adding, when the gate state of the predetermined time slot is the mixed state and when the amount of output delay of the first packet exceeds the allowable amount during output of the second packets, error information to the second packets, outputting the second packets from the second gate, and stopping output of the remaining second packets.

5. The packet processing apparatus according to claim 1 , wherein the controlling includes:

copying, when the gate state of the predetermined time slot is the mixed state and when the amount of output delay of the first packet is within the allowable amount, the second packets in units of packets, outputting the second packets from the second gate, and deleting the copied second packets after the completion of the output of the second packets, and

performing, when the gate state of the predetermined time slot is the mixed state and when the amount of output delay of the first packet exceeds the allowable amount during output of the second packets, a preemption process on the second packets that are being output.

6. The packet processing apparatus according to claim 1 , wherein the controlling includes:

setting, as the priority state, output of the first gate to an open state and output of the second gate to a closed state, and

setting, as the normal state, output of the first gate to the open state and output of the second gate to the open state.

7. A packet processing method performed by a packet processing apparatus that connects, in wired communication, a distributed station and a central station and that comprises:

a first gate that opens and closes output of a first packet in which low delay is requested as compared to a second packet, with respect to the wired communication for each of the time slots in a subframe;

a second gate that opens and closes output of the second packet with respect to the wired communication for each of the time slots in the subframe; and

a processor configured to learn, from a flow rate of the first packet, a cyclic pattern of the first packet for each of the time slot in the subframe in a predetermined cycle; and

the packet processing method comprising:

setting, for each of the time slots as a gate state of each of the first gate and the second gate, a priority state in which the first packet is output with priority, a normal state in which the first packet or the second packet is alternatively output, a mixed state in which the normal state and the priority state are present in a mixed manner;

setting, as a gate state of a predetermined time slot associated with the cyclic pattern, the priority state or the mixed state;

monitoring a flow rate of each of the first packet and the second packet in the predetermined time slot that is set in the mixed state;

determining, from a monitoring result obtained at the monitoring, whether an amount of output delay of the first packet at the time of outputting the first packet and the second packet in the predetermined time slot is within an allowable amount;

allocating, when the amount of output delay of the first packet is within the allowable amount, the first packet and the second packet to the predetermined time slot; and

setting the gate state at output timing of the first packet allocated in the predetermined time slot to the priority state and setting the gate state at output timing of the second packet allocated in the predetermined time slot to the normal state.