IP Library Granted Patent US 11,791,330
Granted Patent B2
US 11,791,330 · App. 17/112,070 · Granted Oct 17, 2023

Electrostatic protection circuit and semiconductor device

Inventor: Tsutomu Tomioka (Tokyo, JP)
Assignee: ABLIC, Inc.
H01L27/0292H01L27/0255H01L27/0266H01L27/0281H01L27/0288H02H9/046
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Quick Facts
Patent No.
US 11,791,330
App. No.
17/112,070
Granted
Oct 17, 2023
Kind
B2
Abstract

An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Claims (27)

1. An electrostatic protection circuit configured to protect a signal terminal of an internal circuit of a semiconductor device, comprising:

a first diode having an anode connected to the signal terminal;

a second diode having a cathode connected to a cathode of the first diode and an anode connected to a GND terminal; and

a depletion type MOS transistor connected in parallel with the first diode, wherein the depletion type MOS transistor is a pMOS transistor having a drain directly connected to at least one of the internal circuit or the anode of the first diode, and having a gate, a source, and a bulk directly connected to the cathode of the first diode.

2. The electrostatic protection circuit according to claim 1 , wherein a resistor is connected between the source of the pMOS transistor and the cathode of the first diode.

3. The semiconductor device comprising:

the electrostatic protection circuit according to claim 2 ;

the internal circuit; and

the signal terminal,

wherein the anode of the first diode and the drain of the pMOS transistor are connected between the signal terminal and the internal circuit.

4. The semiconductor device comprising:

the electrostatic protection circuit according to claim 1 ;

the internal circuit; and

the signal terminal,

wherein the anode of the first diode and the drain of the pMOS transistor are connected between the signal terminal and the internal circuit.

5. The electrostatic protection circuit according to claim 1 , further comprising a gate protection resistor connected between the drain of the pMOS transistor and the anode of the first diode.

6. The semiconductor device comprising:

the electrostatic protection circuit according to claim 5 ;

the internal circuit; and

the signal terminal,

wherein the anode of the first diode, the drain of the pMOS transistor, and the gate protection resistor are all connected between the signal terminal and the internal circuit.

7. The electrostatic protection circuit according to claim 1 , further comprising a gate protection resistor connected between the drain of the pMOS transistor and the internal circuit.

8. The semiconductor device comprising:

the electrostatic protection circuit according to claim 7 ;

the internal circuit; and

the signal terminal,

wherein the anode of the first diode, the drain of the pMOS transistor, and the gate protection resistor are all connected between the signal terminal and the internal circuit.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2020
From: TOMIOKA, TSUTOMU
To: ABLIC INC.
Reel/Frame 054563/0809 →
Priority Claims (1)
JP 2019-233133 · Dec 24, 2019 · national
Continuity (1)
Related Publication 20210193649A1 · Jun 24, 2021