Multi-domain boot and runtime status code drift detection
A method may include, during a first initial boot of a management controller, writing baseline processor domain status information associated with boot of each of a main processor and a second processor of the management controller to a baseline queue, and during each subsequent boot of the management controller, writing run-time processor domain status information associated with boot of each of the main processor and the second processor to a run-time queue, determining if a deviation exists between the run-time queue and the baseline queue, and responsive to the deviation existing between the run-time queue and the baseline queue, taking one or more responsive actions.
1. An information handling system comprising:
a host system comprising a host system processor; and
a management controller communicatively coupled to the host system processor and comprising:
a main management controller processor configured for implementing functionality of the management controller; and
a second management controller processor communicatively coupled to the main management controller processor and configured for implementing additional functionality of the management controller;
wherein, the management controller is configured to:
during a first initial boot of the management controller, write baseline processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a baseline queue; and
during each subsequent boot of the management controller:
write run-time processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a run-time queue;
determine if a deviation exists between the run-time queue and the baseline queue; and
responsive to the deviation existing between the run-time queue and the baseline queue, take one or more responsive actions.
2. The information handling system of claim 1 , wherein the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor.
3. The information handling system of claim 1 , wherein the second management controller processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
4. The information handling system of claim 1 , wherein:
the management controller comprises a third processor;
the management controller is further configured to, during the first initial boot, write baseline processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to the baseline queue;
the management controller is further configured to, during each subsequent boot, write run-time processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to a run-time queue.
5. The information handling system of claim 4 , wherein:
the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor; and
the third processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
6. The information handling system of claim 1 , wherein each of the baseline processor domain status information and the run-time processor domain status information comprise:
power-on/self-test codes generated in connection with boot of the main management controller processor and the second management controller processor; and
timestamps generated in connection with the power-on/self-test codes.
7. The information handling system of claim 1 , wherein the one or more responsive actions comprise:
determining if the deviation is approved by a user/administrator of the information handling system; and
rewriting the baseline processor domain status information with new processing domain status information associated with the current boot processes of the main management controller processor and the second management controller processor.
8. The information handling system of claim 1 , wherein the one or more responsive actions comprise causing a remedial action to be performed responsive to the deviation.
9. A method, in an information handling system comprising a host system comprising a host system processor, the information handling system further comprising a management controller communicatively coupled to the host system processor and having a main management controller processor and configured for implementing functionality of the management controller and a second management controller processor communicatively coupled to the main management controller processor and configured for implementing additional functionality of the management controller, the method comprising:
during a first initial boot of the management controller, writing baseline processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a baseline queue; and
during each subsequent boot of the management controller:
writing run-time processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a run-time queue;
determining if a deviation exists between the run-time queue and the baseline queue; and
responsive to the deviation existing between the run-time queue and the baseline queue, taking one or more responsive actions.
10. The method of claim 9 , wherein the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor.
11. The method of claim 9 , wherein the second management controller processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
12. The method of claim 9 , wherein:
the management controller comprises a third processor; and
the method further comprises:
during the first initial boot, writing baseline processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to the baseline queue; and
during each subsequent boot, writing run-time processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to the run-time queue.
13. The method of claim 12 , wherein:
the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor; and
the third processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
14. The method of claim 9 , wherein each of the baseline processor domain status information and the run-time processor domain status comprise:
power-on/self-test codes generated in connection with boot of the main management controller processor and the second management controller processor; and
timestamps generated in connection with the power-on/self-test codes.
15. The method of claim 9 , wherein the one or more responsive actions comprise:
determining if the deviation is approved by a user/administrator of the information handling system; and
rewriting the baseline processor domain status information with new processing domain status information associated with the current boot processes of the main management controller processor and the second management controller processor.
16. The method of claim 9 , wherein the one or more responsive actions comprise causing a remedial action to be performed responsive to the deviation.
17. An article of manufacture comprising:
a non-transitory computer-readable medium; and
computer-executable instructions carried on the computer-readable medium, the instructions readable by a processing device, the instructions, when read and executed, for causing the processing device to, in an information handling system comprising a host system comprising a host system processor, the information handling system further comprising a management controller communicatively coupled to the host system processor and having a main management controller processor and configured for implementing functionality of the management controller and a second management controller processor communicatively coupled to the main management controller processor and configured for implementing additional functionality of the management controller:
during a first initial boot of the management controller, write baseline processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a baseline queue; and
during each subsequent boot of the management controller:
write run-time processor domain status information associated with boot of each of the main management controller processor and the second management controller processor to a run-time queue;
determine if a deviation exists between the run-time queue and the baseline queue; and
responsive to the deviation existing between the run-time queue and the baseline queue, take one or more responsive actions.
18. The article of claim 17 , wherein the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor.
19. The article of claim 17 , wherein the second management controller processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
20. The article of claim 17 , wherein:
the management controller comprises a third processor; and
the instructions further cause the processing device to:
during the first initial boot, write baseline processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to the baseline queue; and
during each subsequent boot, write run-time processor domain status information associated with boot of each of the main management controller processor, the second management controller processor, and the third processor to the run-time queue.
21. The article of claim 20 , wherein:
the second management controller processor comprises a special-purpose processor used to supplement functionality of the main management controller processor; and
the third processor comprises a cryptoprocessor configured to provide secured boot services and run-time security functions of the management controller.
22. The article of claim 17 , wherein each of the baseline processor domain status information and the run-time processor domain status comprise:
power-on/self-test codes generated in connection with boot of the main management controller processor and the second management controller processor; and
timestamps generated in connection with the power-on/self-test codes.
23. The article of claim 17 , wherein the one or more responsive actions comprise:
determining if the deviation is approved by a user/administrator of the information handling system; and
rewriting the baseline processor domain status information with new processing domain status information associated with the current boot processes of the main management controller processor and the second management controller processor.
24. The article of claim 17 , wherein the one or more responsive actions comprise causing a remedial action to be performed responsive to the deviation.