Memory module with timing-controlled data buffering

1. A memory module operable in a computer system to communicate with a memory controller of the computer system via a memory bus, the memory bus including control and address (C/A) signal lines, data/strobe signal lines, and a clock (CK) signal line, the memory module comprising:

a module board having edge connections corresponding to respective signal lines in the memory bus;

a module control device mounted on the module board, and configurable to receive from the memory controller via the C/A signal lines a read command represented by first input C/A signals, and to output registered C/A signals and module control signals in response to the input C/A signals, the module control device being further configured to receive a system clock signal from the memory controller via the CK signal line and to output a module clock signal;

memory devices mounted on the module board and arranged in a plurality of ranks, wherein, in response to the registered C/A signals, one of the plurality of ranks is configured to output data signals and strobe signals associated with the read command; and

data buffers, wherein:

each respective data buffer of the data buffers is coupled between one or more respective memory devices in each of the plurality of ranks and a respective portion of the edge connections corresponding to a respective section of the data/strobe signal lines, and is configurable, in response to at least some of the module control signals, to receive a respective subset of the data signals and one or more strobe signals corresponding to the respective subset of the data signals from the one or more respective memory devices in the one of the plurality of ranks;

the respective data buffer includes a set of signal paths corresponding, respectively, to the respective subset of the data signals, each signal path of the set of signal paths being configurable to transfer a corresponding data signal of the respective subset of the data signals through the respective data buffer and to add a programmable amount of delay to the corresponding data signal of the respective subset of the data signals, the programmable amount of delay being based on a set of signals associated with a write command and received by the respective data buffer, the write command being represented by second C/A signals that are received by the module control device from the memory controller via the C/A signal lines prior to receiving the read command, the set of signals including one or more signals output from the module control device in response to the second C/A signals.

2. The memory module of claim 1 , wherein the module control signals include signals indicating a mode of operation for the data buffers, signals indicating the one of the plurality of ranks, signals for controlling the set of data paths and one or more ODT signals used by the data buffers to set up on-die termination for the data signals.

3. The memory module of claim 2 , wherein the respective data buffer is further configured to delay at least one of the module control signals received from the module control device by a predetermined amount.

4. The memory module of claim 1 , wherein the respective data buffer is further configured to delay the one or more strobe signals by a programmable amount based on the set of signals.

5. The memory module of claim 1 , wherein the one or more respective memory devices in each of the plurality of ranks correspond to an n-bit section of the memory devices.

6. The memory module of claim 5 , wherein the one or more respective memory devices include one 8-bit-wide memory device or two 4-bit-wide memory devices.

7. The memory module of claim 3 , wherein the respective data buffer further includes respective receiver circuits configurable to receive from the module control device the module control signals, each of the respective receiver circuits including a metastability detection circuit configurable to determine a metastability condition in a received module control signal with respect to a module clock signal.

8. The memory module of claim 1 , wherein the respective data buffer further includes data samplers configurable to sample the respective subset of the data signals using the one or more strobe signals.

9. The memory module of claim 8 , wherein the respective data buffer is further configured to delay the one or more strobe signals by a programmable amount before sampling the respective subset of the data signals using the one or more strobe signals.

10. The memory module of claim 9 , and wherein the respective group of memory devices includes one respective 8-bit-wide memory device or two respective 4-bit-wide memory devices in each of the plurality of ranks.

11. A method, comprising:

at a memory module coupled to a memory controller via a memory bus in a computer system, the memory bus including control and address (C/A) signal lines, data/strobe signal lines, and a clock (CK) signal line, the memory module including a module board having edge connections corresponding to respective signal lines in the memory bus, a module control device mounted on the module board, memory devices mounted on the module board and arranged in a plurality of ranks, and data buffers coupled between respective n-bit sections of the memory devices and respective portions of the edge connections corresponding to respective n-bit sections of the data bus, each respective n-bit section of the memory devices including one or more respective memory devices in each of the plurality of ranks,

receiving, at the module control device, a read command represented by first input C/A signals from the memory controller via the C/A signal lines and a system clock signal from the memory controller via the CK signal line;

outputting, from the module control device, registered C/A signals and module control signals in response to the input C/A signals, and a module clock signal in response to the system clock signal;

outputting, from one of the plurality of ranks and in response to the registered C/A signals, data signals and strobe signals associated with the read command;

receiving, at the data buffers, the module control signals and the module clock signal from the module control device;

receiving, at each respective data buffer of the data buffers, a respective subset of the data signals and one or more strobe signals corresponding to the respective subset of the data signals from one or more respective memory devices in the one of the plurality of ranks; and

transferring the respective subset of the data signals through the respective data buffer, wherein the respective data buffer includes a set of signal paths corresponding, respectively, to the respective subset of the data signals, and each respective signal path of the set of signal paths is configurable to transfer a corresponding data signal of the respective subset of the data signals through the respective data buffer and to add a programmable amount of delay to the corresponding data signal of the respective subset of the data signals, the programmable amount of delay being based on a set of signals associated with a write command and received by the respective data buffer, the write command being represented by second C/A signals that are received by the module control device from the memory controller via the C/A signal lines prior to receiving the read command, the set of signals including one or more signals output from the module control device in response to the second C/A signals.

12. The method of claim 11 , wherein the module control signals include signals indicating a mode of operation for the data buffers, signals indicating the one of the plurality of ranks, signals for controlling the set of data paths and one or more CDT signals used by the data buffers to set up on-die termination for the data signals.

13. The method of claim 12 , further comprising delaying at least one of the module control signals received from the module control device by a predetermined amount at the respective data buffer.

14. The method of claim 11 , further comprising, delaying the one or more strobe signals by a programmable amount based on one or more of the set of signals.

15. The method of claim 11 , wherein each n-bit section of the memory devices includes one respective 8-bit-wide memory device or two respective 4-bit-wide memory devices in each of the plurality of ranks.

16. The method of claim 11 , wherein receiving, at the data buffers, the module control signals from the module control device includes determining a metastability condition in a received module control signal with respect to a module clock signal.

17. The method of claim 11 , wherein transferring the respective subset of the data signals through the respective data buffer includes:

sampling each data signal of the respective subset of the data signals using a corresponding one of the one or more strobe signals.

18. The method of claim 17 , further comprising delaying the one or more strobe signals by a programmable amount before sampling the respective subset of the data signals using the one or more strobe signals.

19. The method of claim 18 , wherein each n-bit section of the memory devices includes one respective 8-bit-wide memory device or two respective 4-bit-wide memory devices in each of the plurality of ranks.

20. A memory module operable in a computer system to communicate with a memory controller of the computer system via a memory bus, the memory bus including control and address (C/A) signal lines, data/strobe signal lines, and a clock (CK) signal line, the memory module comprising:

a module board having edge connections corresponding to signal lines in the memory bus;

a module control device mounted on the module board, and configurable to receive from the memory controller via the C/A signal lines first input C/A signals corresponding to a write command and subsequently second input C/A signals corresponding to a read comment, and to output first module control signals in response to the first input C/A signals, and subsequently second module control signals in response to the second input C/A signals, the module control device being further configured to receive a system clock signal from the memory controller via the CK signal line and to output a module clock signal;

memory devices mounted on the module board and arranged in a plurality of ranks; and

data buffers coupled between respective byte-wise sections of the memory devices and respective portions of the edge connections corresponding to respective byte-wise sections of the data/strobe signal lines, and configurable to receive from the module control device the first module control signals and subsequently the second module control signals in addition to the module clock signal, wherein:

each byte-wise section of the memory devices includes one respective 8-bit-wide memory device or two respective 4-bit-wide memory devices in each of the plurality of ranks;

one of the plurality of ranks is configured to output data signals and strobe signals associated with the read command;

each respective data buffer of the data buffers is further configurable, in response to at least some of the second module control signals, to receive a respective subset of the data signals and one or more strobe signals corresponding to the respective subset of the data signals from one or two respective memory devices in the one of the plurality of ranks, and includes a set of signal paths corresponding, respectively, to the respective subset of the data signals, each respective signal path of the set of signal paths being configurable to transfer a corresponding data signal of the respective subset of the data signals through the respective data buffer and to add a programmable amount of delay to the corresponding data signal of the respective subset of the data signals, the programmable amount of delay being based on a set of signals associated with the write command and received by the respective data buffer, the set of signals including at least one of the first module control signals.