Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

1. An apparatus, comprising:

a memory including:

a temperature sensor configured to provide temperature information indicative of a temperature;

programmable termination resistances having a programmable impedance; and

an impedance calibration circuit configured to perform a calibration operation to arbitrate with another memory for use of an external resistance and determine calibration parameters for setting the programmable impedance of the programmable termination resistances based on the temperature information provided by the temperature sensor.

2. The apparatus of claim 1 , wherein the impedance calibration circuit is configured to perform the calibration operation based on the temperature information responsive to a change in the temperature exceeding a temperature range.

3. The apparatus of claim 1 , wherein the impedance calibration circuit is configured to perform the calibration operation based on the temperature information responsive to the temperature exceeding a temperature limit.

4. The apparatus of claim 1 , wherein the impedance calibration circuit comprises:

an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters; and

an impedance calibration controller configured to initiate the calibration operation, the impedance calibration controller comprising:

impedance calibration control logic configured to provide a calibration activation signal to activate the impedance calibration engine; and

a temperature comparator configured to receive the temperature information and cause the impedance calibration control logic to activate the impedance calibration engine.

5. The apparatus of claim 1 , wherein the impedance calibration circuit comprises:

an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters; and

an impedance calibration controller configured to initiate the calibration operation, the impedance calibration controller comprising:

impedance calibration control logic configured to provide a calibration activation signal to activate the impedance calibration engine; and

a timer configured to cause the impedance calibration control logic to activate the impedance calibration engine responsive to a time period elapsing.

6. The apparatus of claim 1 , wherein the programmable termination resistances comprise:

adjustable pull-down termination components configured to provide a pull-down impedance that is adjustable based on pull-down calibration parameters; and

adjustable pull-up termination components configured to provide a pull-up impedance that is adjustable based on pull-up calibration parameters.

7. A method comprising:

determining a change in temperature based, at least in part, by comparing a previous temperature to a current temperature;

determining whether the change in temperature exceeds a temperature range;

initiating a calibration operation of a memory when the change in temperature exceeds the temperature range;

arbitrating with one or more other memory devices for use of an external resistance, with an arbitration engine of the memory;

obtaining control of the external resistance, and

performing the calibration operation after control of the external resistance is obtained.

8. The method of claim 7 , further comprising latching the current temperature by a calibration circuit.

9. The method of claim 7 , wherein the current temperature is provided as a voltage level, wherein the voltage level corresponds to a temperature measured by a temperature sensor.

10. The method of claim 9 , wherein the voltage level increases when the temperature measured by the temperature sensor increases and the voltage level decreases when the temperature measured by the temperature sensor decreases.

11. The method of claim 7 , further comprising programming the temperature range in a mode register.

12. The method of claim 11 , wherein programming the temperature range in the mode register comprises programming a first temperature range and a second temperature range in the mode register.

13. The method of claim 7 , wherein the calibration operation comprises:

performing ZQ calibration to determine calibration results for output driver impedance; and

setting a value in a mode register at completion of the ZQ calibration to indicate if a new calibration result has been determined.

14. An apparatus comprising:

impedance calibration control logic configured to provide a calibration activation signal to initiate a ZQ calibration operation;

a temperature comparator configured to receive temperature information and cause the impedance calibration control logic to activate the calibration activation signal when the temperature information indicates a change in temperature exceeds a temperature range; and

a calibration flag circuit configured to program calibration information into a mode register.

15. The apparatus of claim 14 , further comprising a timer configured to receive a clock signal and cause the impedance calibration control logic to activate the calibration activation signal when a time period has elapsed.

16. The apparatus of claim 14 , wherein the calibration information indicates whether the calibration information is completed.

17. The apparatus of claim 14 , wherein the temperature comparator is further configured to latch the temperature information, wherein the temperature information is associated with a voltage signal provided by a temperature sensor.

18. The apparatus of claim 14 , wherein the temperature comparator is further configured to compare latched temperature information to previously latched temperature information to determine the change in temperature.

19. The apparatus of claim 14 , wherein the impedance calibration control logic is further configured to receive a calibration signal from a command decoder.

20. The apparatus of claim 4 , wherein the impedance calibration circuit further comprises an arbitration engine configured to arbitrate with the other memory for the use of the external resistance.