Circuit structure and method for reducing electronic noises

1. A method for semiconductor fabrication, comprising:

providing a semiconductor structure including a substrate, an isolation region on the substrate, and an active region that is at least partially surrounded by the isolation region;

forming a gate stack over a channel region of the active region, the gate stack including a gate dielectric layer and a gate electrode layer disposed above the gate dielectric layer;

forming a source and a drain on the active region such that the channel region is disposed between the source and the drain along a first direction;

forming a low density doped (LDD) feature adjacent the gate stack along a second direction perpendicular to the first direction, wherein the LDD feature separates an edge portion of the gate dielectric layer from the isolation region; and

after the forming of the LDD feature, forming a spacer on sidewalls of the gate stack and directly above the LDD feature.

2. The method of claim 1 ,

wherein the edge portion of the gate dielectric layer is between two corner portions of the gate dielectric layer,

wherein the LDD feature does not separate the two corner portions of the gate stack from the isolation region, and

wherein the two corner portions of the gate dielectric layer extend laterally into the isolation region.

3. The method of claim 1 , further comprising forming a high density doped (HDD) feature that separates the LDD feature and the spacer from the isolation region.

4. The method of claim 3 ,

wherein the LDD feature and the HDD feature are formed on a first side of the gate stack, and

wherein the method further comprises forming a second LDD feature but no additional HDD feature on a second side of the gate stack opposite to the first side of the gate stack.

5. The method of claim 3 ,

wherein the LDD feature and the HDD feature are formed using separate ion implantation processes, wherein the LDD feature has a doping concentration at least twice as high as that of a channel region underneath the gate stack, and

wherein the HDD feature includes a doping concentration that is at least 10 times as high as that of the LDD feature.

6. The method of claim 3 ,

wherein a doping concentration of a channel region underneath the gate stack is between 1*E13 per square centimeter and 5*E13 per square centimeter,

wherein a doping concentration of the LDD feature is between 6*E13 per square centimeter and 9*E13 per square centimeter, and

wherein a doping concentration of the HDD feature is greater than 1*E15 per square centimeter.

7. The method of claim 3 , further comprising:

forming a source in the active region, the source being at a first distance from the gate stack; and

forming a drain in the active region, the drain being at a second distance from the gate stack,

wherein the gate stack is sandwiched between the source and the drain,

wherein the second distance is greater than the first distance.

8. The method of claim 7 ,

wherein the LDD feature, and the HDD feature comprise a first type dopant,

wherein the source and the drain comprise a second type dopant different from the first type dopant.

9. A method, comprising:

providing a semiconductor structure that includes:

a substrate,

an active region disposed on the substrate and comprising a first portion, a second portion and a middle portion disposed between the first portion and the second portion along a first direction, wherein the middle portion has a protruded region that extends beyond the first and the second portions along a second direction perpendicular to the first direction, and

an isolation region at least partially surrounding the active region;

forming a gate stack over the active region and extending along the second direction, the gate stack including four corner portions that laterally extend beyond the active region into the isolation region and the gate stack including a center portion that laterally extend within the protruded region;

forming a low density doped (LDD) feature that separates an edge portion of the gate stack from the isolation region along the second direction; and

forming a spacer on sidewalls of the gate stack directly above the LDD feature.

10. The method of claim 9 ,

wherein each of the first portion and the second portion includes a first width along the second direction and the middle portion includes a second width along the second direction,

wherein the second width is greater than the first width.

11. The method of claim 9 ,

wherein the edge portion of the gate stack is disposed between two of the four corner portions of the gate stack, wherein the LDD feature does not separate the two of the four corner portions of the gate stack from the isolation region.

12. The method of claim 9 , further comprising forming a high density doped (HDD) feature that separates the LDD feature from the isolation region.

13. The method of claim 12 ,

wherein the LDD feature and the HDD feature are formed using separate ion implantation processes,

wherein the LDD feature has a doping concentration at least twice as high as that of a channel region underneath the gate stack.

14. The method of claim 13 , wherein the HDD feature includes a doping concentration that is at least 10 times as high as that of the LDD feature.

15. The method of claim 12 , further comprising:

epitaxially growing a source feature over the first portion of the active region; and

epitaxially growing a drain feature over the second portion of the active region,

wherein the gate stack is sandwiched between the source feature and the drain feature along the first direction.

16. The method of claim 15 ,

wherein the source feature is at a first distance from the gate stack along the second direction,

wherein the drain feature is at a second distance from the gate stack along the second direction,

wherein the second distance is greater than the first distance.

17. The method of claim 15 ,

wherein the LDD feature, and the HDD feature comprise a first type dopant,

wherein the source feature and the drain feature comprise a second type dopant different from the first type dopant.

18. A method, comprising:

providing a semiconductor structure that includes:

a substrate,

an active region disposed on the substrate and comprising a first portion, a second portion and a middle portion disposed between the first portion and the second portion along a first direction, wherein each of the first portion and the second portion includes a first width along a second direction perpendicular to the first direction and the middle portion includes a second width along the second direction, wherein the second width is greater than the first width, and

an isolation region at least partially surrounding the active region;

forming a gate stack over the active region, wherein the gate stack has a first length in the first direction and the middle portion of the active region has a second length in the first direction, wherein the first length is greater than the second length such that four corner portions of the gate stack laterally extend beyond the active region into the isolation region;

forming a first low density doped (LDD) feature that separates a first edge of the gate stack from the isolation region along the second direction and a second LDD feature that separates a second edge of the gate stack from the isolation region along the second direction; and

forming a spacer on sidewalls of the gate stack, wherein the spacer is directly above the first LDD feature and the second LDD feature.

19. The method of claim 18 , further comprising forming a high density doped (HDD) feature to separate one of the first LDD feature and the second LDD feature from the isolation region.

20. The method of claim 19 ,

wherein the first LDD feature and the second LDD feature comprise a doping concentration at least twice as high as that of a channel region underneath the gate stack, and

wherein the HDD feature includes a doping concentration that is at least 10 times as high as the doping concentration of the LDD feature.