Testing hardware in a quantum computing system
In a general aspect, quantum computing system performance is tested. Systems and methods for testing hardware in a quantum computing system are described. The methods may include certification/decertification of data produced by the quantum computing system, detection of faults, correction of errors and/or recalibration/replacement of the quantum computing system or a quantum computing subsystem.
1. A method for identifying a presence of one or more faults in a quantum processor cell of a hybrid computing environment, the hybrid computing environment comprising classical control hardware, a classical processor coupled to the classical control hardware, and the quantum processor cell, the method comprising:
by operation of the classical processor,
defining a test domain in the hybrid computing environment, the test domain comprising a set of qubits of the quantum processor cell and corresponding classical control hardware;
defining a target distribution over measured bit patterns for the test domain;
producing a control sequence, configured to generate the target distribution;
executing the control sequence on the set of qubits and the corresponding classical control hardware to produce output bit patterns in the test domain;
recording the output bit patterns;
repeating the executing and recording;
calculating correlations between the output bit patterns to generate at least one figure of merit; and
evaluating the at least one figure of merit to determine a likelihood of the presence of one or more faults.
2. The method of claim 1 , wherein the test domain comprises a subset of the set of qubits and corresponding classical control hardware.
3. The method of claim 1 , wherein the target distribution is given by multiple measurement bit patterns obtained for an entangled state in the test domain.
4. The method of claim 3 , wherein the entangled state is a Greenberger-Horne-Zeilinger (GHZ)-type state.
5. The method of claim 1 , wherein the target distribution allows for performing Bell tests of the qubits in the test domain.
6. The method of claim 1 , wherein the control sequence includes digital control information for execution on the classical control hardware.
7. The method of claim 1 , wherein the measured bit patterns are obtained by measuring one or more of the qubits in the test domain.
8. The method of claim 1 , wherein the calculating correlations includes computing statistical correlations between the output bit patterns, wherein the at least one figure of merit is obtained by comparing the correlations of the output bit patterns with the correlations of an ideally prepared target distribution.
9. The method of claim 1 , further comprising:
evaluating one or more of the at least one figure of merit against a criterion; and
reporting a fault if the at least one figure of merit does not meet the criterion.
10. The method of claim 9 , further comprising, if a fault is reported, conducting a recalibration of the hybrid computing environment.
11. The method of claim 9 , further comprising, if a fault is reported, subdividing the test domain to better determine where the fault originated.
12. The method of claim 1 , further comprising:
evaluating the at least one figure of merit against a criterion; and
decertifying data produced by the hybrid computing environment since a most recent prior hybrid computing environment test if the at least one figure of merit does not meet the criterion.
13. The method of claim 1 , further comprising:
evaluating the at least one figure of merit against a criterion; and
certifying data produced by the hybrid computing environment within a timeframe as accurate if the at least one figure of merit meets the criterion.
14. The method of claim 1 , wherein the calculating correlations includes computing statistical correlations between the output bit patterns, wherein the at least one figure of merit is obtained by comparing the correlations of the output bit patterns with the correlations of a target distribution for a system known to be operating correctly.
15. The method of claim 1 , wherein the method for identifying the presence of faults in the hybrid computing environment is run in parallel with user-submitted hybrid computing programs on the quantum processor cell.
16. The method of claim 1 , wherein the method for identifying the presence of faults in the hybrid computing environment is run interleaved with user-submitted hybrid computing programs on the quantum processor cell.
17. The method of claim 1 , wherein the method for identifying the presence of faults in the hybrid computing environment is incorporated in a user-submitted hybrid computing program.
18. The method of claim 1 , comprising:
performing repeated Ramsey measurements for detection of changes in electromagnetic environment of the quantum processor cell that lead to shifts of qubit transition frequencies or decreased coherence times.
19. A hybrid computing environment, comprising:
a quantum processor cell comprising a plurality of qubit devices;
classical control hardware comprising controllers and signal hardware coupled to the quantum processor cell for operating components in the quantum processor cell; and
a classical processor coupled to the classical control hardware and configured to perform operations, comprising;
defining a test domain in the quantum processor cell, the test domain comprising a set of qubits in the quantum processor cell and corresponding components of the classical control hardware;
defining a target distribution over measured bit patterns for the test domain;
producing a control sequence, configured to generate the target distribution;
executing the control sequence to produce output bit patterns in the test domain of the quantum processor cell;
recording the output bit patterns;
repeating the executing and recording;
calculating correlations between the output bit patterns to generate at least one figure of merit; and
evaluating the at least one figure of merit to determine a likelihood of a presence of one or more faults.
20. The hybrid computing environment of claim 19 , wherein the classical processor is located on a host server of the hybrid computing environment.
21. The hybrid computing environment of claim 19 , wherein the classical processor is located on an access node of the hybrid computing environment.
22. The hybrid computing environment of claim 19 , wherein the classical processor is a component of the classical control hardware.
23. The hybrid computing environment of claim 19 , wherein the operations comprise:
performing repeated Ramsey measurements for detection of changes in electromagnetic environment of the quantum processor cell that lead to shifts of qubit transition frequencies or decreased coherence times.