Semiconductor memory device and manufacturing method thereof
A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.
1. A method for manufacturing a semiconductor memory device, comprising:
forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area;
forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area;
removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area, by injecting an etching solution for removing the second dielectric layers through the slits; and
forming electrode layers in spaces from which the second dielectric layers are removed.
2. The method according to claim 1 , further comprising, after the forming of the electrode layers:
forming contact plugs through the first and second dielectric layers in the center of the connection area.
3. The method according to claim 1 , wherein the second dielectric layers are formed of a dielectric material having an etching selectivity with respect to the first dielectric layers.