Apparatus for processing biomedical signals for display
Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.
1. A system for displaying electrocardiogram (ECG) and intracardiac (IC) signals, comprising:
a Wilson Central Terminal (WCT) circuit configured to be coupled to three limb electrodes;
a right-leg drive (RLD) circuit configured to be coupled to a fourth limb electrode; and
a twin-T network, coupled to the RLD circuit, comprising a first twin-T circuit coupled to a second twin-T circuit and an operational amplifier;
wherein a node of the first twin-T circuit is coupled to a first input of the operational amplifier, at least two of the three limb electrodes are coupled to a second input of the operational amplifier, and an output of the operational amplifier is coupled to an input of the RLD circuit, and
wherein a node of the second twin-T circuit is coupled to the output of the operational amplifier.
2. The system of claim 1 , wherein the WCT circuit provides a unipolar input reference for single catheter inputs.
3. The system of claim 1 , wherein the RLD circuit is configured to remove common mode voltage from a signal received at the input of the RLD circuit.
4. The system of claim 1 , wherein the RLD circuit is configured to prevent current having an amplitude greater than one microampere from flowing to the fourth limb electrode.
5. The system of claim 1 , wherein the twin-T network comprises a notch filter in a feedback path of the twin-T network.
6. The system of claim 1 , wherein the twin-T network is configured to provide enhanced common mode rejection of a first harmonic frequency and a third harmonic frequency of power mains.
7. The system of claim 1 , wherein a first harmonic frequency is 60 Hz and a third harmonic frequency is 180 Hz.
8. The system of claim 1 , wherein the RLD circuit is configured to remove a common mode voltage from a signal received from the three limb electrodes.
9. The system of claim 1 , wherein the twin-T network is configured to produce a first peak and a second peak at the output of the operational amplifier, wherein the first peak has a first center frequency located at a first harmonic frequency and the second peak has a second center frequency located at a third harmonic frequency.