Global shutter pixel circuit and method for computer vision applications

1. An image sensor device, comprising:

a plurality of pixel cells arranged in a pixel array;

a control circuit for controlling an exposure phase and a sampling phase of the image sensor device; and

a switching circuit for coupling a pixel power supply line to a first voltage in an exposure phase and to a second voltage in a sampling phase, the first voltage being higher than the second voltage;

wherein each of the plurality of pixel cells comprises:

a photodiode in a semiconductor substrate, a first end of the photodiode coupled to a bias voltage through a shutter gate controlled by a global shutter signal;

a ground contact for coupling a second end of the photodiode to an electrical ground through an electrical ground conductive line;

a storage diode in the semiconductor substrate and coupled to a second end of the photodiode through a first transfer gate controlled by a first transfer signal; and

a floating diffusion region in the semiconductor substrate and coupled to the storage diode through a second transfer gate controlled by a second transfer signal.

2. The image sensor device of claim 1 , wherein the control circuit is configured to activate the photodiode in a plurality of time windows to sense light reflected from a target as a result of a corresponding plurality of emitted light pulses, with a pre-determined delay time between each time window and a corresponding emitted light pulse.

3. The image sensor device of claim 2 , further comprising a drain region, wherein:

a first end of the photodiode is coupled to a bias voltage through the drain region; and

the control circuit is configured to provide a plurality of bias voltage pulses to activate the photodiode in the plurality of time windows to sense reflected light.

4. The image sensor device of claim 2 , wherein the control circuit is configured to provide a plurality of global shutter signal pulses to activate the photodiode in the plurality of time windows to sense reflected light.

5. A pixel cell for time-of-flight (ToF) distance measurement, comprising:

a substrate;

a photodiode;

a ground contact for coupling a second end of the photodiode to an electrical ground through an electrical ground conductive line;

a drain region adjacent to the photodiode and coupled to a bias voltage;

a shutter gate disposed between the photodiode and the drain region, the shutter gate controlled by a global shutter signal to apply the bias voltage to bias the photodiode for light sensing;

a storage diode coupled to the photodiode through a first transfer gate controlled by a first transfer signal; and

a floating diffusion region coupled to the storage diode through a second transfer gate controlled by a second transfer signal.

6. The pixel cell of claim 5 , wherein:

the photodiode is formed in a rectangular diffusion area having four side lines;

the shutter gate is disposed along a first side line between the photodiode and the drain region, the shutter gate having a same length as the first side line; and

the first transfer gate is disposed along a second side line adjacent the first side line, the first transfer gate having a length that is half the length of the second side line and disposed over a corner of the photodiode away from the first side line.

7. The pixel cell of claim 5 , further comprising first, second, and third metal interconnect layers, wherein: a first transfer line, a second transfer line, a select line, and a reset line are formed in the first metal interconnect layer along a first direction, and span a total width of W; a voltage supply VDDA line, a voltage supply VSSA line, and a pixel output line are formed in the second metal interconnect layer along a second direction perpendicular to the first direction; and a global shutter line is formed in the third metal interconnect layer along the first 8 direction, the global shutter line having a width substantially equal to W.

8. The pixel cell of claim 5 , wherein the drain region comprises a low capacitance drain diffusion region to facilitate modulating of the bias voltage.