IP Library Granted Patent US 11,594,969
Granted Patent B2
US 11,594,969 · App. 17/138,050 · Granted Feb 28, 2023

Non-inverting buck-boost converter

Inventor: Antonio Remetio Soleno (Mandaluyong, PH)
Assignee: Astec International Limited
H02M3/1582H02M1/0025
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Quick Facts
Patent No.
US 11,594,969
App. No.
17/138,050
Granted
Feb 28, 2023
Kind
B2
Abstract

A buck-boost converter circuit, such as a non-inverting buck-boost converter, can include two separate control loop circuits to separately control operation of the buck circuit and the boost circuit. The control loop circuits may include two different voltage reference signals, two different current reference signals, two different current feedback signals, two different voltage feedback signals, or a combination thereof. The buck-boost converter circuit can operate in three modes: a buck mode, a transition mode, and a boost mode.

Claims (44)

1. A buck-boost converter circuit comprising:

an input configured to receive an input voltage;

an output configured to provide an output voltage;

a buck circuit having a first power switch and a first power diode coupled between the input and a ground reference;

a boost circuit having a second power switch and a second power diode coupled between the output and the ground reference;

a first feedback control circuit coupled between the output and the buck circuit, the first feedback control circuit configured to switch the buck circuit on and off based on a first reference voltage;

a second feedback control circuit coupled between the output and the boost circuit, the second feedback control circuit configured to switch the boost circuit on and off based on a second reference voltage; and

the first feedback control circuit and the second feedback control circuit are configured to avoid overlap operation of both the buck circuit and the boost circuit during a transition from a buck mode to a boost mode and vice versa;

wherein the first feedback control circuit comprises:

a first summation circuit configured to produce a first summation output that is a sum of a first peak current and a buck slope compensation value;

a first comparator configured to receive the first reference voltage and a feedback voltage based on the output voltage as inputs to the first comparator;

a second comparator configured to receive an output of the first comparator and the first summation output as inputs to the second comparator to generate a duty cycle at the output of the second comparator;

the second feedback control circuit including:

a second summation circuit configured to produce a second summation output that is a sum of a second peak current and a boost slope compensation value;

a third comparator configured to receive the second reference voltage and the feedback voltage based on the output voltage as inputs to the third comparator; and

a fourth comparator configured to receive an output of the third comparator and the second summation output as inputs to the second comparator to generate a duty cycle at the output of the second comparator.

2. A buck-boost converter circuit comprising:

an input configured to receive an input voltage;

an output configured to provide an output voltage;

a buck circuit having a first power switch and a first power diode coupled between the input and a ground reference;

a boost circuit having a second power switch and a second power diode coupled between the output and the ground reference;

a first feedback control circuit coupled between the output and the buck circuit, the first feedback control circuit configured to switch the buck circuit on and off based on a first reference voltage, the first feedback control circuit including:

a first comparator configured to receive the first reference voltage and a feedback voltage based on the output voltage as inputs to the first comparator; and

a second comparator configured to receive an output of the first comparator and an average current of the output voltage as inputs to the second comparator;

a third comparator configured to receive an output of the second comparator and a sawtooth signal as inputs to the second comparator to generate a duty cycle for the first power switch;

a second feedback control circuit coupled between the output and the boost circuit, the second feedback control circuit configured to switch the boost circuit on and off based on a second reference voltage, the second feedback control circuit including:

a fourth comparator configured to receive the second reference voltage and the feedback voltage based on the output voltage as inputs to the fourth comparator;

a fifth comparator configured to receive an output of the fourth comparator and the average current of the output voltage as inputs to the fifth comparator; and

a sixth comparator configured to receive an output of the fifth comparator and a sawtooth signal as inputs to the sixth comparator to generate a duty cycle for the second power switch;

wherein the first feedback control circuit and the second feedback control circuit are configured to avoid overlap operation of both the buck circuit and the boost circuit during a transition from a buck mode to a boost mode and vice versa.

3. A buck-boost converter circuit comprising:

an input configured to receive an input voltage;

an output configured to provide an output voltage;

a buck circuit having a first power switch and a first power diode coupled between the input and a ground reference;

a boost circuit having a second power switch and a second power diode coupled between the output and the ground reference;

a first feedback control circuit coupled between the output and the buck circuit, the first feedback control circuit configured to switch the buck circuit on and off based on a first feedback voltage and a first reference voltage, the first feedback control circuit including:

a first comparator configured to receive the first feedback voltage and the first reference voltage as inputs to the first comparator;

a second comparator configured to receive an output of the first comparator and a sawtooth signal as inputs to the second comparator to generate a duty cycle signal at the output of the second comparator for the first power switch; and

a first transistor configured to provide the output of the first comparator to either the second comparator or to ground;

a second feedback control circuit coupled between the output and the boost circuit, the second feedback control circuit configured to switch the boost circuit on and off based on a second feedback voltage and the first reference voltage, the second feedback control circuit including:

a third comparator configured to receive the second feedback voltage and the first reference voltage as inputs to the third comparator; and

a fourth comparator configured to receive an output of the third comparator and a sawtooth signal as inputs to the fourth comparator to generate a duty cycle signal at the output of the second comparator for the second power switch; and

a second transistor configured to provide the output of the third comparator to either the fourth comparator or to ground;

wherein the first feedback control circuit and the second feedback control circuit are configured to avoid overlap operation of both the buck circuit and the boost circuit during a transition from a buck mode to a boost mode and vice versa.

Assignments (2)
CONFIRMATORY PATENT ASSIGNMENT Recorded Mar 5, 2025
From: ASTEC INTERNATIONAL LIMITED
To: AES GLOBAL HOLDINGS PTE. LTD.
Reel/Frame 070404/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2021
From: SOLENO, ANTONIO REMETIO
To: ASTEC INTERNATIONAL LIMITED
Reel/Frame 055800/0979 →