IP Library Granted Patent US 12,442,902
Granted Patent B2
US 12,442,902 · App. 17/143,570 · Granted Oct 14, 2025

Pipelined histogram pixel

Inventors: Robert Henderson (Edinburgh, GB); Tarek Al Abbas (Edinburgh, GB); David Storrar (Falkirk, GB)
Assignee: Sense Photonics, Inc.
G01S7/4865G01S7/4815G01S7/4816G01S17/894G01S17/931
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Quick Facts
Patent No.
US 12,442,902
App. No.
17/143,570
Granted
Oct 14, 2025
Kind
B2
Abstract

A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a first memory and a second memory, and at least one control circuit. The at least one control circuit is configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal. Related devices and methods of operation are also discussed.

Claims (47)

1. A Light Detection and Ranging (LIDAR) detector circuit, comprising:

a non-transitory memory device comprising a first memory and a second memory; and

at least one control circuit configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal,

wherein the first portion of the time comprises a strobe window of activation of the one or more photodetector elements, wherein the detection signals are output from the one or more photodetector elements in response to a plurality of photons incident thereon during the strobe window,

wherein the second portion of the time comprises a remainder of the time between the pulses of the emitter signal, after the strobe window and before a next pulse of the pulses of the emitter signal, and

wherein the first memory is a buffer memory device and the second memory is a main memory device, and wherein the at least one control circuit is further configured to execute the second memory storage operations to transfer the data from the buffer memory to be included in the main memory after the strobe window and before the next pulse of the emitter signal.

2. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit comprises a sampler circuit that is configured to execute the first memory storage operations, and wherein the first memory storage operations comprise sampling the data from the detection signals at a predetermined sampling rate and writing the data to respective bins of the first memory.

3. The LIDAR detector circuit of claim 2 , wherein the at least one control circuit further comprises a memory controller that is configured to execute the second memory storage operations, and wherein the second memory storage operations comprise retrieving the data from the respective bins of the first memory and integrating the data into respective bins of the second memory, wherein the respective bins of the second memory comprise histogram data for an imaging distance subrange corresponding to the strobe window.

4. The LIDAR detector circuit of claim 3 , wherein the memory controller and the second memory are inactive during the first portion of the time, and wherein the sampler circuit is inactive during the second portion of the time.

5. The LIDAR detector circuit of claim 4 , wherein the second memory comprises static random access memory (SRAM) or a dynamic random access memory (DRAM), and wherein the second memory storage operations comprise precharge and read operations to retrieve the data from the respective bins of the first memory, and precharge, read, modify, and write operations to integrate the data into the respective bins of the second memory.

6. The LIDAR detector circuit of claim 1 , further comprising:

a detector interface circuit coupled to the at least one control circuit and configured to receive the detection signals from the one or more photodetector elements during the first portion of the time, wherein the detector interface circuit is inactive during the second portion of the time.

7. The LIDAR detector circuit of claim 1 , wherein:

the one or more photodetector elements comprise a subset of a plurality of photodetector elements, and respective subsets of the plurality of photodetector elements define respective detector pixels; and

the at least one control circuit comprises a shared control circuit that is configured to execute the first memory storage operations for the respective detector pixels during the first portion of the time, and is configured to execute the second memory storage operations for the respective detector pixels during the second portion of the time.

8. The LIDAR detector circuit of claim 7 , wherein the second memory comprises respective main memory devices, and wherein the shared control circuit is configured to execute the second memory storage operations to store respective data for the respective detector pixels in the respective main memory devices sequentially during the second portion of the time.

9. The LIDAR detector circuit of claim 7 , wherein the first memory comprises respective buffer memory devices, and wherein the shared control circuit is configured to execute the first memory storage operations to store respective data for the respective detector pixels in the respective buffer memory devices in parallel during the first portion of the time.

10. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit is configured to execute the first memory storage operations responsive to a first clock signal, and to execute the second memory storage operations responsive to a second clock signal different than the first clock signal.

11. The LIDAR detector circuit of claim 1 , wherein the one or more photodetector elements comprise single-photon avalanche detectors (SPADs), and wherein the data comprises photon counts indicated by the detection signals corresponding to an imaging distance subrange defined by the strobe window.

12. A Light Detection and Ranging (LIDAR) detector circuit, comprising:

one or more photodetector elements defining a LIDAR detector pixel;

a buffer memory device;

a main memory device; and

at least one processor circuit configured to execute first and second memory storage operations to store data indicated by detection signals received from the LIDAR detector pixel in the buffer and main memory devices during first and second portions of a time between pulses of a LIDAR emitter signal, respectively,

wherein the first portion of the time comprises a strobe window of activation of the LIDAR detector pixel, and the second portion of the time comprises a remainder of the time between the pulses of the LIDAR emitter signal, after the strobe window and before a next pulse of the pulses of the LIDAR emitter signal, and

wherein data is transferred from the buffer memory to the main memory after a strobe window of activation of the one or more photodetector elements and before the next pulse of the emitter signal.

13. The LIDAR detector circuit of claim 12 , wherein the at least one processor circuit comprises:

a sampler circuit that is configured to execute the first memory storage operations to sample the data from the detection signals at a predetermined sampling rate and write the data to respective bins of the buffer memory device; and

a memory controller that is configured to execute the second memory storage operations to retrieve the data from the respective bins of the buffer memory device and integrate the data in respective bins of the main memory device, wherein the respective bins of the main memory device comprise histogram data for an imaging distance subrange corresponding to the strobe window.

14. The LIDAR detector circuit of claim 13 , wherein the memory controller and the main memory are inactive during the first portion of the time, and wherein the sampler circuit is inactive during the second portion of the time.

15. The LIDAR detector circuit of claim 14 , wherein:

the one or more photodetector elements define a respective LIDAR detector pixel of a plurality of LIDAR detector pixels, each of the LIDAR detector pixels being associated with a respective buffer memory device and a respective main memory device; and

the at least one processor circuit comprises a shared control circuit that is configured to execute the first memory storage operations for each of the LIDAR detector pixels in parallel to store respective data indicated by detection signals received therefrom in the respective buffer memory device, and to execute the second memory storage operations for each of the LIDAR detector pixels sequentially to include the respective data in the respective main memory device.

16. The LIDAR detector circuit of claim 12 , wherein the at least one processor circuit is configured to execute the first and second memory storage operations responsive to different first and second clock signals, respectively.

17. A method of operating a Light Detection and Ranging (LIDAR) detector circuit, the method comprising:

executing first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in a first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element; and

executing second memory storage operations to include the data, which was stored in the first memory, in a second memory during a second portion of the time between the pulses of the emitter signal,

wherein the first portion of the time comprises a strobe window of activation of the one or more photodetector elements, and wherein the detection signals are received from the one or more photodetector elements in response to a plurality of photons incident thereon during the strobe window,

wherein the second portion of the time comprises a remainder of the time between the pulses of the emitter signal, after the strobe window and before a next pulse of the pulses of the emitter signal, and

wherein data is transferred from the first memory to the second memory after a strobe window of activation of the one or more photodetector elements and before the next pulse of the emitter signal.

18. The method of claim 17 , wherein:

the executing the first memory storage operations comprises sampling the data from the detection signals at a predetermined sampling rate and writing the data to respective bins of the first memory; and

the executing the second memory storage operations comprise retrieving the data from the respective bins of the first memory and integrating the data in respective bins of the second memory, wherein the respective bins of the second memory comprise histogram data for an imaging distance subrange corresponding to the strobe window.

19. The method of claim 17 , wherein the executing the first and second memory storage operations comprises:

executing the first memory storage operations responsive to a first clock signal; and

executing the second memory storage operations responsive to a second clock signal different than the first clock signal.

20. A LIDAR system comprising the LIDAR detector circuit of claim 1 , wherein the LIDAR system is configured to be coupled to an autonomous vehicle such that the LIDAR emitter element and the one or more photodetector elements are oriented relative to an intended direction of travel of the autonomous vehicle.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADD THE SECOND ASSIGNEE PREVIOUSLY RECORDED AT REEL: 65350 FRAME: 826. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 29, 2023
From: HERCULES CAPITAL, INC.
To: OUSTER, INC.; SENSE PHOTONICS, INC.
Reel/Frame 066432/0458 →
RELEASE OF INTELLECTUAL PROPERTY SECURITY INTEREST AT REEL/FRAME NO. 059859/0035 Recorded Oct 25, 2023
From: HERCULES CAPITAL, INC.
To: OUSTER, INC.
Reel/Frame 065350/0826 →
SECURITY INTEREST Recorded Apr 29, 2022
From: OUSTER, INC.; SENSE PHOTONICS, INC.
To: HERCULES CAPITAL, INC., AS AGENT
Reel/Frame 059859/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2021
From: THE UNIVERSITY COURT OF THE UNIVERSITY OF EDINBURGH
To: SENSE PHOTONICS, INC.
Reel/Frame 055127/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2021
From: AL ABBAS, TAREK; STORRAR, DAVID
To: SENSE PHOTONICS, INC.
Reel/Frame 054861/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2021
From: HENDERSON, ROBERT
To: THE UNIVERSITY COURT OF THE UNIVERSITY OF EDINBURGH
Reel/Frame 054861/0405 →
Continuity (2)
Provisional Application 62958894 · Jan 9, 2020
Related Publication 20210215807A1 · Jul 15, 2021
References Cited (20)
US 10914824B2 · Meng et al. · 2021 [cited by applicant]
US 20120075615A1 · Niclass et al. · 2012 [cited by applicant]
US 20130088620A1 · Centen · 2013 [cited by examiner]
US 20140253758A1 · Metz · 2014 [cited by applicant]
US 20150145518A1 · Haldner · 2015 [cited by examiner]
US 20170052065A1 · Sharma et al. · 2017 [cited by applicant]
US 20180164415A1 · Buckley et al. · 2018 [cited by applicant]
US 20180209846A1 · Mandai et al. · 2018 [cited by applicant]
US 20180301872A1 · Burroughs et al. · 2018 [cited by applicant]
US 20190250257A1 · Finkelstein et al. · 2019 [cited by applicant]
US 20200135776A1 · Finkelstein · 2020 [cited by applicant]
US 20200225333A1 · Birnbacher · 2020 [cited by examiner]
CN 109814117A · 2019 [cited by applicant]
EP 3460508A1 · 2019 [cited by applicant]
Extended European Search Report corresponding to European Patent Application No. 21738192.0 (12 pages) (dated Oct. 30, 2023). [cited by applicant]
Niclass et al. “A 0.18μm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensor” IEEE Journal of Solid-State Circuits, 49(1):315-330 (2014). [cited by applicant]
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, in corresponding PCT Application No. PCT/US2021/012458 (Apr. 29, 2021). [cited by applicant]
U.S. Appl. No. 62/966,171 entitled “DRAM-Based LIDAR Pixel” filed Jan. 27, 2020. [cited by applicant]
CN202180008472.X , “Office Action”, May 30, 2025, 19 pages. [cited by applicant]
EP21738192.0 , “Intention to Grant”, May 21, 2025, 8 pages. [cited by applicant]