Copper-alloy capping layers for metallization in touch-panel displays
In various embodiments, electronic devices such as touch-panel displays incorporate interconnects featuring a conductor layer and, disposed above the conductor layer, a capping layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni.
1. A method of forming an electronic device, the method comprising:
providing a substrate;
depositing over the substrate a barrier layer (i) comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni, and (ii) comprising a plurality of crystalline grains separated by grain boundaries;
depositing over the barrier layer a conductor layer comprising at least one of Cu, Ag, Al, or Au;
forming a mask layer over the barrier layer and the conductor layer;
patterning the mask layer to reveal a portion of the conductor layer;
thereafter, applying an etchant to remove portions of the conductor layer and the barrier layer not masked by the patterned mask layer, thereby forming a sidewall comprising (i) an exposed portion of the barrier layer, (ii) an exposed portion of the conductor layer, and (iii) an interface between the exposed portion of the barrier layer and the exposed portion of the conductor layer; and
annealing the substrate at a temperature sufficient to form a particulate within at least one of the grain boundaries, the particulate comprising at least one of (i) an agglomeration of at least one of the refractory metal elements or (ii) a reaction product of silicon and at least one of the refractory metal elements.
2. The method of claim 1 , wherein, after the etchant is applied, the sidewall is substantially free of discontinuities notwithstanding the interface.
3. The method of claim 1 , wherein the etchant comprises a mixture of phosphoric acid, acetic acid, nitric acid, and water.
4. The method of claim 1 , wherein the barrier layer comprises an alloy of Ta and Cu.
5. The method of claim 1 , wherein the barrier layer comprises an alloy of Nb and Cu.
6. The method of claim 1 , wherein the barrier layer comprises an alloy of Ta, Zr, and Cu.
7. The method of claim 1 , wherein the barrier layer comprises an alloy of Cu, Ta, and Ti.
8. The method of claim 1 , wherein the substrate comprises glass.
9. The method of claim 1 , wherein the substrate comprises silicon.
10. The method of claim 9 , wherein the substrate comprises amorphous silicon.
11. The method of claim 1 , further comprising removing the remaining portion of the patterned mask layer.
12. An electronic device comprising:
a substrate; and
a conductive feature disposed over the substrate, the conductive feature comprising:
(i) disposed on the substrate, a barrier layer (i) comprising an alloy of Cu and one or more refractory metal elements selected from the list consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni, and (ii) comprising a plurality of crystalline grains separated by grain boundaries, and
(ii) disposed on the barrier layer, a conductor layer comprising at least one of Cu, Ag, Al, or Au,
wherein at least one of the grain boundaries comprises a particulate therein, the particulate comprising at least one of (i) an agglomeration of at least one of the refractory metal elements or (ii) a reaction product of silicon and at least one of the refractory metal elements.
13. The electronic device of claim 12 , wherein the barrier layer comprises an alloy of Ta and Cu.
14. The electronic device of claim 12 , wherein the barrier layer comprises an alloy of Nb and Cu.
15. The electronic device of claim 12 , wherein the barrier layer comprises an alloy of Ta, Zr, and Cu.
16. The electronic device of claim 12 , wherein the barrier layer comprises an alloy of Cu, Ta, and Ti.
17. The electronic device of claim 12 , wherein (i) the conductor layer comprises Cu, and (ii) the substrate is substantially free of Cu diffusion from the conductor layer.
18. The electronic device of claim 12 , wherein the substrate comprises glass.
19. The electronic device of claim 12 , wherein the substrate comprises silicon.
20. The electronic device of claim 12 , wherein the substrate comprises amorphous silicon.
21. The electronic device of claim 12 , wherein the conductive feature comprises an electrode.