Granted Patent B2

US 12,373,167 · App. 17/148,850 · Granted Jul 29, 2025

Inventor: Loren J. Swenson (San Jose, CA)

Assignee: 1372934 B.C. LTD.

G06F7/22G06N10/20G06N10/40G06N10/60H03H11/04H03H11/36

Abstract

Claims (29)

1. A filter multiplexer system comprising:

at least one external annealing line;

a plurality of filters communicatively coupled to the at least one external annealing line, each filter of the plurality of filters having a different cutoff frequency; and

a multiplexer, the multiplexer having an output line and a plurality of input lines, each input line in the plurality of input lines communicatively coupled to one filter in the plurality of filters, and a plurality of pathways, each pathway comprising at least one superconducting switch.

2. The system of claim 1 wherein the at least one superconducting switch is a cryotron.

3. The system of claim 1 further comprising a plurality of external annealing lines, each external annealing line communicatively coupled to a respective one filter in the plurality of filters.

4. The system of claim 1 further comprising the output line of the multiplexer communicatively coupled to at least one on-chip annealing line, the on-chip annealing line communicatively coupled to qubits of a quantum processor.

5. The system of claim 1 , further comprising a demultiplexer, the demultiplexer having one input line, communicatively coupled to the at least one external annealing line, and a plurality of output lines, each output line in the plurality of output lines communicatively coupled to one filter in the plurality of filters, the demultiplexer comprising a plurality of pathways, each pathway comprising at least one superconducting switch.

6. The system of claim 5 wherein the at least one superconducting switch is a cryotron.

7. A system for variable annealing bandwidth selection comprising:

a quantum annealing processor, the quantum annealing processor comprising a plurality of qubits and couplers, and a set of on-chip annealing lines, the on-chip annealing lines communicatively coupled to the plurality of qubits;

at least one external annealing line;

a plurality of filters communicatively coupled to the at least one external annealing line, each filter of the plurality of filters having a different cutoff frequency; and

a multiplexer, the multiplexer having an output line and a plurality of input lines, each input line in the plurality of input lines communicatively coupled to the at least one filter in the plurality of filters, and a plurality of pathways, each pathway comprising at least one superconducting switch.

8. The system of claim 7 wherein the quantum annealing processor, the plurality of filters and the multiplexer are housed at a same temperature as one another.

9. The system of claim 7 , wherein the at least one superconducting switch is a cryotron.

10. The system of claim 7 further comprising a plurality of external annealing lines, each external annealing line communicatively coupled to a respective one filter in the plurality of filters.

11. The system of claim 7 further comprising the output line of the multiplexer communicatively coupled to at least one on-chip annealing line of the set of on-chip annealing lines.

12. The system of claim 7 , further comprising a demultiplexer, the demultiplexer having one input line, communicatively coupled to the at least one external annealing line, and a plurality of output lines, each output line in the plurality of output lines communicatively coupled to a respective one filter in the plurality of filters, the demultiplexer comprising a plurality of pathways, each pathway comprising at least one superconducting switch.

13. A method for variable bandwidth annealing in a quantum annealing processor system comprising a quantum annealing processor, the quantum annealing processor comprising a plurality of qubits, and a set of on-chip annealing lines, the on-chip annealing lines communicatively coupled to the plurality of qubits; at least one external annealing line; a plurality of filters communicatively coupled to the at least one external annealing line, at least two of the plurality of filters having a different cutoff frequency from one another; and a multiplexer, the multiplexer having an output line and a plurality of input lines, the output line of the multiplexer communicatively coupled to the on-chip annealing lines, each input line in the plurality of input lines communicatively coupled to the at least one filter in the plurality of filters, and a plurality of pathways, each pathway comprising at least one superconducting switch, the multiplexer able to provide a plurality of annealing bandwidth settings, the method comprising:

setting an annealing bandwidth setting via the multiplexer; and

causing the quantum processor to evolve according to the annealing bandwidth setting.

14. The method of claim 13 further comprising receiving an input problem, the input problem having a desired annealing schedule; and wherein setting an annealing bandwidth setting to obtain the desired annealing schedule occurs before causing the quantum processor to evolve according to the set annealing bandwidth.

15. A method for calibrating a quantum annealing processor system comprising a quantum annealing processor, the quantum annealing processor comprising a plurality of qubits, and a set of on-chip annealing lines, the on-chip annealing lines communicatively coupled to the plurality of qubits; at least one external annealing line; a plurality of filters communicatively coupled to the at least one external annealing line, each filter of the plurality of filters having a different cutoff frequency from one another; and a multiplexer, the multiplexer having an output line and a plurality of input lines, the output line of the multiplexer communicatively coupled to the on-chip annealing lines, each input line in the plurality of input lines communicatively coupled to the at least one filter in the plurality of filters, and a plurality of pathways, each pathway comprising at least one superconducting switch, the multiplexer able to provide a plurality of annealing bandwidth settings, the method comprising:

setting a large annealing bandwidth setting via the multiplexer; and

performing a calibration of the quantum processor while causing the quantum processor to evolve according to the large annealing bandwidth setting.

16. The method of claim 15 , further comprising: iteratively, until all available annealing bandwidth settings have been set,

selecting an i th annealing bandwidth setting via the multiplexer; and

performing a calibration of the quantum processor while causing the quantum processor to evolve according to the i th annealing bandwidth setting.

Assignments (14)

Continuity (2)

References Cited (299)

Cited By (1)

US 12,705,525