IP Library Granted Patent US 11,709,626
Granted Patent B2
US 11,709,626 · App. 17/148,872 · Granted Jul 25, 2023

Scheduling storage system tasks to promote low latency and sustainability

Inventors: Vladimir Shveidel (Pardes-Hana, IL); Ronen Gazit (Tel Aviv, IL)
Assignee: EMC IP Holding Company LLC
G06F3/0659G06F3/0611G06F3/0673
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Quick Facts
Patent No.
US 11,709,626
App. No.
17/148,872
Granted
Jul 25, 2023
Kind
B2
Abstract

A technique for scheduling access to a resource arranges tasks into multiple classes, where each class has a respective share and a respective priority. The share of a class sets an amount of access allocated to the class, and the priority sets an order in which the class can use its share, with higher priority classes getting access before lower-priority classes. The technique assigns latency-critical tasks, such as synchronous I/O tasks, to a first class having the highest priority and assigns bandwidth-critical tasks, such as background I/O processing, to a second class having a lower priority.

Claims (44)

1. A method of scheduling tasks to be run on a computing resource in a data storage system, comprising:

arranging tasks into multiple classes, the classes having respective shares and respective priorities;

assigning latency-critical tasks to a first class and bandwidth-critical tasks to a second class; and

running tasks by the computing resource in priority order, with the latency-critical tasks of the first class running before the bandwidth critical tasks of the second class, and with the first class and the second class each allocated access to the computing resource in accordance with their respective shares,

wherein the method further comprises running multiple scheduling cycles in succession, wherein the first class and the second class are allocated access to the computing resource in accordance with their respective shares within the scheduling cycles,

wherein the latency-critical tasks assigned to the first class include I/O request tasks for receiving and responding to I/O requests but not background I/O tasks for incorporating data received in I/O write requests into persistent storage structures, and wherein bandwidth-critical tasks assigned to the second class include background I/O tasks for incorporating data received in I/O write requests into persistent storage structures but not I/O request tasks for receiving and responding to I/O requests, and

wherein the act of scheduling tasks is itself a task and is assigned to the second class.

2. The method of claim 1 , wherein the classes further include a third class for additional background tasks, the third class having a lowest priority.

3. The method of claim 2 , wherein the shares of the first class and the shares of the second class together account for 100% of a scheduling cycle, with a share of the third class being zero.

4. The method of claim 3 , wherein tasks in the third class are run in response to both the first class and the second class having no tasks ready to be run.

5. The method of claim 3 , wherein the share of the second class is provided as an adjustable parameter, with the share of the first class being dependent upon the share of the second class.

6. The method of claim 5 , wherein the share of no other class besides the second class is an adjustable parameter.

7. The method of claim 5 , further comprising monitoring progress of tasks in the second class and changing the share of the second class in response to detecting that the progress differs from a target level.

8. The method of claim 7 , wherein changes in the share of the second class are rate-limited.

9. The method of claim 2 , further comprising reassigning a set of tasks in the third class to the second class in response to determining that the set of tasks has become critical.

10. The method of claim 1 , wherein a lower-priority class exceeds its allocated share within a scheduling cycle in response to no higher-priority class having any tasks ready to be run.

11. A computerized apparatus, comprising control circuitry that includes a set of processing units coupled to memory, the control circuitry constructed and arranged to:

arrange tasks into multiple classes, the classes having respective shares and respective priorities;

assign latency-critical tasks to a first class and bandwidth-critical tasks to a second class; and

run tasks by a computing resource in priority order, with the latency-critical tasks of the first class running before the bandwidth critical tasks of the second class, and with the first class and the second class each allocated access to the computing resource in accordance with their respective shares,

wherein the control circuitry is further constructed and arranged to run multiple scheduling cycles in succession, wherein the first class and the second class are allocated access to the computing resource in accordance with their respective shares within the scheduling cycles,

wherein the latency-critical tasks assigned to the first class include I/O request tasks for receiving and responding to I/O requests but not background I/O tasks for incorporating data received in I/O write requests into persistent storage structures, and wherein bandwidth-critical tasks assigned to the second class include background I/O tasks for incorporating data received in I/O write requests into persistent storage structures but not I/O request tasks for receiving and responding to I/O requests, and

wherein scheduling of tasks is itself a task and is assigned to the second class.

12. A computer program product including a set of non-transitory, computer-readable media having instructions which, when executed by control circuitry of a computerized apparatus, cause the computerized apparatus to perform a method of scheduling tasks to be run on a computing resource, the method comprising:

arranging tasks into multiple classes, the classes having respective shares and respective priorities;

assigning latency-critical tasks to a first class and bandwidth-critical tasks to a second class; and

running tasks by the computing resource in priority order, with the latency-critical tasks of the first class running before the bandwidth critical tasks of the second class, and with the first class and the second class each allocated access to the computing resource in accordance with their respective shares,

wherein the method further comprises running multiple scheduling cycles in succession, wherein the first class and the second class are allocated access to the computing resource in accordance with their respective shares within the scheduling cycles,

wherein the latency-critical tasks assigned to the first class include I/O request tasks for receiving and responding to I/O requests but not background I/O tasks for incorporating data received in I/O write requests into persistent storage structures, and wherein bandwidth-critical tasks assigned to the second class include background I/O tasks for incorporating data received in I/O write requests into persistent storage structures but not I/O request tasks for receiving and responding to I/O requests, and

wherein the act of scheduling tasks is itself a task and is assigned to the second class.

13. The computer program product of claim 12 ,

wherein the classes further include a third class for additional background tasks, the third class having a lowest priority.

14. The computer program product of claim 13 ,

wherein the shares of the first class and the shares of the second class together account for 100% of a scheduling cycle, with a share of the third class being zero, and

wherein tasks in the third class are run in response to both the first class and the second class having no tasks ready to be run.

15. The computer program product of claim 12 ,

wherein the share of the second class is provided as an adjustable parameter, with the share of the first class being dependent upon the share of the second class, and

wherein the share of no other class besides the second class is an adjustable parameter.

16. The method of claim 1 , wherein the multiple tasks further include a third class for additional background tasks, wherein the share of the second class is provided as an adjustable parameter, with the share of the first class depends solely upon the share of the second class.

17. The method of claim 1 , wherein running tasks by the computing resource in priority order includes:

running first tasks of the first class within a scheduling cycle responsive to the first class having shares remaining in the scheduling cycle; and

running second tasks of the second class within the scheduling cycle responsive to second class having shares remaining in the scheduling cycle and there being no pending first tasks of the first class with shares of the first class remaining in the scheduling cycle.

18. The method of claim 17 , wherein the classes further include a third class for additional background tasks, the third class having a lowest priority, and wherein running tasks by the computing resource in priority order further includes:

running third tasks of the third class within the scheduling cycle responsive to there being (i) no pending first tasks of the first class with shares of the first class remaining and (ii) no pending second tasks of the second class with shares of the second class remaining.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (055479/0342) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 062021/0460 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (055479/0051) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 062021/0663 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056136/0752) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 062021/0771 →
RELEASE OF SECURITY INTEREST AT REEL 055408 FRAME 0697 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0553 →
SECURITY INTEREST Recorded Mar 3, 2021
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056136/0752 →
SECURITY INTEREST Recorded Mar 3, 2021
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 055479/0051 →
SECURITY INTEREST Recorded Mar 3, 2021
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 055479/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2021
From: SHVEIDEL, VLADIMIR; GAZIT, RONEN
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 055443/0068 →
SECURITY AGREEMENT Recorded Feb 25, 2021
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 055408/0697 →
Continuity (1)
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