Information processing apparatus and non-transitory computer readable medium
An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: upon initialization, reconfigure a first region of the programmable logic circuit as a first memory that stores data; reconfigure a second region different from the first region of the programmable logic circuit as a first arithmetic circuit that uses the first memory; and, in a case where the second region reconfigured as the first arithmetic circuit is reconfigured as a second arithmetic circuit different from the first arithmetic circuit, allow the second arithmetic circuit to use the first memory.
1. An information processing apparatus comprising:
a processor connected to a programmable logic circuit, the processor being configured to:
upon initialization, reconfigure a first region of the programmable logic circuit as a first memory that stores data;
reconfigure a second region different from the first region of the programmable logic circuit as a first arithmetic circuit that uses the first memory; and
in a case where the second region reconfigured as the first arithmetic circuit is reconfigured as a second arithmetic circuit different from the first arithmetic circuit, allow the second arithmetic circuit to use the first memory.
2. The information processing apparatus according to claim 1 , wherein the processor is configured not to reconfigure the first region except for upon the initialization of the programmable logic circuit.
3. The information processing apparatus according to claim 2 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, if a storage capacity of the first memory used by the first arithmetic circuit is insufficient, reconfigure a third region of the programmable logic circuit as a second memory that supplements the storage capacity.
4. The information processing apparatus according to claim 3 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to the first memory.
5. The information processing apparatus according to claim 4 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
6. The information processing apparatus according to claim 2 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to the first memory.
7. The information processing apparatus according to claim 6 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
8. The information processing apparatus according to claim 2 , wherein the processor is configured to:
when the second region is reconfigured as the first arithmetic circuit, if a storage capacity of the first memory used by the first arithmetic circuit is insufficient, reconfigure a third region of the programmable logic circuit as a second memory that supplements the storage capacity; and
reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to each of the first memory and the second memory.
9. The information processing apparatus according to claim 8 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
10. The information processing apparatus according to claim 1 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, if a storage capacity of the first memory used by the first arithmetic circuit is insufficient, reconfigure a third region of the programmable logic circuit as a second memory that supplements the storage capacity.
11. The information processing apparatus according to claim 10 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to the first memory.
12. The information processing apparatus according to claim 11 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
13. The information processing apparatus according to claim 1 , wherein the processor is configured to, when the second region is reconfigured as the first arithmetic circuit, reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to the first memory.
14. The information processing apparatus according to claim 13 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
15. The information processing apparatus according to claim 14 , wherein the fourth region is adjacent to the first region.
16. The information processing apparatus according to claim 1 , wherein the processor is configured to:
when the second region is reconfigured as the first arithmetic circuit, if a storage capacity of the first memory used by the first arithmetic circuit is insufficient, reconfigure a third region of the programmable logic circuit as a second memory that supplements the storage capacity; and
reconfigure a fourth region of the programmable logic circuit as a control circuit that controls access from the first arithmetic circuit to each of the first memory and the second memory.
17. The information processing apparatus according to claim 16 , wherein a distance between the fourth region and the first region is less than a distance between the second region and the first region.
18. The information processing apparatus according to claim 1 , wherein:
the programmable logic circuit includes a plurality of logic blocks arranged in a grid pattern, and
the second region is rectangular.
19. The information processing apparatus according to claim 18 , wherein the first region has a predetermined unified width.
20. A non-transitory computer readable medium storing a program causing a computer including a processor connected to a programmable logic circuit to execute a process, the process comprising:
upon initialization, reconfiguring a first region of the programmable logic circuit as a first memory that stores data;
reconfiguring a second region different from the first region of the programmable logic circuit as a first arithmetic circuit that uses the first memory; and
in a case where the second region reconfigured as the first arithmetic circuit is reconfigured as a second arithmetic circuit different from the first arithmetic circuit, allowing the second arithmetic circuit to use the first memory.