Vector population count determination via comparsion iterations in memory
Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.
1. A method, comprising:
determining, using sensing circuitry, a vector population count of a number of elements of a vector stored in a memory array by:
performing a number of comparison iterations, wherein performing the number of comparison iterations comprises:
determining a reduction vector for each of the number of comparison iterations, wherein determining the reduction vector includes determining a reduction vector width for each of the number of comparison iterations and wherein each of the number of comparison iterations compares a number of bits that correspond to the reduction vector width;
determining a pattern mask for each of the number of comparison iterations; and
performing a half add operation of a first portion and a second portion of the pattern mask for each of the number of comparison iterations.
2. The method of claim 1 , comprising determining a quantity of comparison iterations to perform by calculating logy of a number of bits in each of the number of elements.
3. The method of claim 1 , comprising determining an elemental mask for the vector, wherein the elemental mask represents a most significant bit of each of the number of elements.
4. The method of claim 1 , wherein performing the number of comparison iterations includes comparing 2 n bits during each respective comparison iteration.
5. The method of claim 1 , wherein performing the number of comparison iterations includes performing a loop that includes shifting a carry of the half add operation to the left one place, and checking for carry values using a BlockOR operation, and performing another half add operation with the shift carry values and a sum of the half add operation.
6. An apparatus comprising:
a group of memory cells coupled to a first access line of a memory array and configured to store a number of elements; and
a controller configured to:
perform a number of comparison iterations, wherein each of the number of comparison iterations includes determining a reduction vector for each of the number of comparison iterations, wherein determining the reduction vector includes determining a reduction vector width for each of the number of comparison iterations and wherein each of the number of comparison iterations compares a number of bits that correspond to the reduction vector width, determining a pattern mask for each of the number of comparison iterations, and performing a half add operation of a first portion and a second portion of the pattern mask for each of the number of comparison iterations; and
output a vector population count that indicates how many bits of each of the number of elements have a particular data value in response to performing the number of comparison iterations.
7. The apparatus of claim 6 , wherein the controller is configured to determine the number of comparison iterations to perform by calculating logy of a number of bits in the number of elements.
8. The apparatus of claim 6 , wherein the controller is configured to calculate an output for each of the number of comparison iterations that is used by a subsequent comparison iteration to determine the vector population count.
9. The apparatus of claim 6 , wherein the controller is configured to perform at least one of an AND operation, an OR operation, and a SHIFT operation using sensing circuitry to determine the vector population count.
10. An apparatus, comprising:
a group of memory cells coupled to a first access line of a memory array and configured to store a vector comprising a number of elements; and
a controller configured to:
perform at least one of an AND operation, an OR operation, and a SHIFT operation using sensing circuitry to determine a vector population count of the number of elements by:
determining a reduction vector for each of a number of comparison iterations, wherein determining the reduction vector includes determining a reduction vector width for each of the number of comparison iterations and wherein each of the number of comparison iterations compares a number of bits that correspond to the reduction vector width;
determining a pattern mask for each of the number of comparison iterations, wherein each of the pattern masks include a first portion of the pattern mask and a second portion of the pattern mask; and
perform a half add operation on the first portion of the pattern mask and the second portion of the pattern mask for each of the number of comparison iterations.
11. The apparatus of claim 10 , wherein the sensing circuitry comprises a sense amplifier and a compute component.
12. The apparatus of claim 11 , wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.
13. The apparatus of claim 10 , wherein the sensing circuitry is configured to determine a most significant bit of each of the number of elements.
14. The apparatus of claim 10 , wherein the sensing circuitry is configured to store elements representing a most significant bit of each of the number of elements as an elemental mask.
15. The apparatus of claim 10 , wherein the sensing circuitry is configured to determine the number of comparison iterations to perform by calculating logy of a number of bits in the number of elements.