IP Library Granted Patent US 11,706,891
Granted Patent B2
US 11,706,891 · App. 17/151,365 · Granted Jul 18, 2023

Perceptible indicators of wires being attached correctly to controller

Inventors: Troy Aaron Harvey (Salt Lake City, UT); Jeremy David Fillingim (Salt Lake City, UT)
H05K7/1465F24F11/32F24F11/49F24F11/63F24F11/88G01R31/55G05B13/0265G05B15/02G05B19/048G05B23/0216G05B23/0264G05B23/0272G06F1/3209G06F1/3246G06F3/0482G06F3/04186G06F3/04847G06F3/147G06F8/436G06F8/51G06F8/53G06F8/74G06F9/4418G06F30/12G06F30/13G06F30/18G06Q30/0283H02J3/00H04B3/46H04L43/50H04L67/12H04L67/125H04L67/75H04M3/305H04W4/80H04W84/00H05K7/1468H05K7/1477H05K7/1481G06F30/392G06F2111/04G06F2111/16G06F2113/04G06F2113/16G06F2115/12H02J2310/12
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,706,891
App. No.
17/151,365
Granted
Jul 18, 2023
Kind
B2
Abstract

Tools and techniques are described to automate line testing when wiring devices (such as equipment and sensors) to controllers. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. After testing, a reporting device rapidly shows the results of the line testing.

Claims (33)

1. A controller comprising: line testing technology, a processor, a memory comprising: a database of proposed device-controller locations, and a database of device layouts, the device layouts associated with devices operationally able to be wired to the controller, the device layouts comprising wiring pin layout; the line testing technology interacting with the processor and the memory to perform, upon execution, a process which includes:

detecting that a device wire has been coupled to the controller at a controller location;

pairing a device layout with a proposed device controller location using the database of proposed device-controller locations;

determining validity of the device wire with respect to the device layout; and

reporting the determined validity.

2. The controller of claim 1 wherein determining validity of the device wire further comprises the controller operationally able to determine at least one of: voltage on the device wire; current on the device wire; protocol on the device wire, signal received from the device wire in response to a signal sent by the controller, or fault on the device wire.

3. The controller of claim 1 , further comprising the controller operationally able to turn on a device associated with the device wire and operationally able to determine how much power is being drawn.

4. The controller of claim 3 , further comprising the controller able to determine voltage on a device wire when the device associated with that device wire is turned off.

5. The controller of claim 1 , further comprising a wiring pin on the controller associated with the controller location; wherein the controller is operationally able to change characteristics of the wiring pin.

6. The controller of claim 5 , wherein controller operationally able to change characteristics of the wiring pin comprises a module associated with controller modifying hardware associated with the wiring pin.

7. The controller of claim 6 , wherein the controller is operationally able to attach to a module, and wherein the module is operationally able to attach to the device wire.

8. The controller of claim 7 , wherein the module further comprises operational ability to determine a voltage, a current, a signal, or a fault.

9. The controller of claim 1 , wherein the controller operationally able to report determined validity further comprises a light signaling when the device wire is valid.

10. The controller of claim 1 , wherein the line testing technology comprises at least one of: a ground connection, a 24 VAC power connection, a DAC with 0-10V DC analog voltage, a FET with a 1-wire pullup, a high range voltage divider, a low range voltage divider, a 4-20 mA current shunt, a 24 VAC current shunt, a DC offset injector, an electromechanical relay, a 120 VAC output, a current-measuring chip, a control for high current motors, or a feature that can switch 250 volt AC up to 10 amps.

11. A method performed by a controller for line testing a device, the method comprising:

noticing a device has been operably attached to a wiring pin;

determining desired device from a device database of the controller;

determining a wiring feature of the desired device from the device database;

determining validity of the wiring feature with reference to the wiring pin; and

reporting the validity using a reporting feature of the controller.

12. The method of claim 11 , wherein the reporting feature comprises a light associated with the wiring pin.

13. The method of claim 11 , wherein a module is associated with with a controller connector, and further comprising associating the wiring pin with the module.

14. The method of claim 13 , further comprising the controller determining wiring type of the device using the device database.

15. The method of claim 14 , further comprising the module changing wiring pin type to match wiring type of the device.

16. The method of claim 15 , wherein the module comprises a processor, memory, software, a plurality of wiring pin types available in hardware, and wherein the module modifies wiring pin type by receiving a signal from the controller, then uses the software to activate a wiring pin type.

17. The method of claim 16 , wherein the wiring feature comprises a wiring fault, a power, a voltage, a current, or a protocol.

18. The method of claim 12 , wherein reporting the validity using the reporting feature comprises turning on the light associated with the wiring pin.

19. A non-transitory computer-readable storage medium configured with instructions for execution by a processor which upon execution performs a method of line testing a device, the method comprising:

instructions for noticing that a device has been operably attached to a wiring pin;

instructions for determining desired device from a device database;

instructions for determining a wiring feature of the desired device from the device database;

instructions for determining validity of the wiring feature with reference to the wiring pin; and

instructions for reporting the validity using an I/O device.

Assignments (2)
SECURITY INTEREST Recorded Nov 19, 2025
From: PASSIVELOGIC, INC.; QUANTUM ALLIANCE LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 073605/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2021
From: HARVEY, TROY AARON; FILLINGIM, JEREMY DAVID
To: PASSIVELOGIC, INC.
Reel/Frame 054945/0091 →
Continuity (2)
Provisional Application 63070460 · Aug 26, 2020
Related Publication 20220069863A1 · Mar 3, 2022
Cited By (1)
US 12,408,287