Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
1. A flash memory device comprising:
a plurality of flash memory cells, each flash memory cell comprising a single transistor, said single transistor being a floating gate transistor;
a p-well coupled to the plurality of flash memory cell transistors and configured to be biased to a positive well bias voltage for an erase operation;
a plurality of main word lines, each main word line of the plurality of main word lines coupled to a corresponding group of local word lines, each local word line coupled to gate terminals of the floating gate transistors of corresponding ones of the plurality of flash memory cells; and
driver circuit configured to:
in the erase operation:
pass a first negative word line voltage on a selected main word line of the plurality of main word lines to at least one selected local word line; and
pass a positive word line voltage on unselected main word lines of the plurality of main word lines to a plurality of unselected local word lines;
and then, in a soft program operation:
pass a second negative word line voltage different from the first negative word line voltage on the unselected main word lines of the plurality of main word lines to the plurality of unselected local word lines.
2. The flash memory device of claim 1 , wherein the driver circuit is further configured to, in the soft program operation, pass the second negative word line voltage on the selected main word line of the plurality of main word lines to the at least one selected local word line.
3. The flash memory device of claim 1 , wherein the difference between the positive well bias voltage and the first negative word line voltage is sufficient to erase selected flash memory cells connected to the at least one selected local word line.
4. The flash memory device of claim 1 , wherein the difference between the positive well bias voltage and the positive word line voltage is insufficient to erase unselected flash memory cells connected to the plurality of unselected local word lines.
5. The flash memory device of claim 1 , wherein the positive well bias voltage is higher than VCC.
6. The flash memory device of claim 5 , wherein the positive well bias voltage is approximately 7.5 volts.
7. The flash memory device of claim 1 , wherein the first negative word line voltage is higher in magnitude than VCC.
8. The flash memory device of claim 7 , wherein the first negative word line voltage is approximately −7.5 volts.
9. The flash memory device of claim 1 , wherein the second negative word line voltage is lower in magnitude than VCC.
10. The flash memory device of claim 9 , wherein the second negative word line voltage is approximately −0.5 volts or −1.0 volts.
11. The flash memory device of claim 1 , wherein the positive word line voltage is lower in magnitude than VCC.
12. The flash memory device of claim 11 , wherein the positive word line voltage is approximately 2.5 volts.
13. The flash memory device of claim 1 , wherein the plurality of flash memory cell transistors are NAND type flash memory cell transistors.
14. The flash memory device of claim 1 , wherein the plurality of flash memory cell transistors are NOR type flash memory cell transistors.
15. The flash memory device of claim 1 , wherein the plurality of flash memory cells corresponds to a first block of a plurality of erasable blocks, each block associated with a p-well;
wherein each of the plurality of main word lines in the first block corresponds to one of a plurality of erasable sectors of flash memory cells in that block.
16. The flash memory device of claim 1 , wherein each of the plurality of main word lines corresponds to one of a plurality of erasable sectors of flash memory cells in the p-well.
17. The flash memory device of claim 1 , wherein the driver circuit further configured to pass a second positive word line voltage on the selected main word line of the plurality of main word lines to the at least one selected local word line for a program operation.
18. The flash memory device of claim 17 , wherein the driver circuit further configured to pass the second negative word line voltage on the unselected main word lines of the plurality of main word lines to the plurality of unselected local word lines for the program operation.
19. The flash memory device of claim 17 , wherein the second positive word line voltage is higher in magnitude than VCC.
20. The flash memory device of claim 19 , wherein the second positive word line voltage is approximately 8 volts.