Low-power voltage regulator with fast transient response

1. A voltage regulator, comprising:

a pass device coupled between an input of the voltage regulator and an output of the voltage regulator;

an amplifying circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifying circuit is coupled to a gate of the pass device;

a first current source coupled between a supply rail and the amplifying circuit, wherein the first current source comprises a first transistor coupled between the supply rail and the amplifying circuit and a drain of the first transistor is coupled directly to the amplifying circuit, wherein a capacitor is coupled between a gate of the first transistor and the output of the voltage regulator;

a second current source coupled between the supply rail and the amplifying circuit, wherein the second current source comprises a second transistor coupled between the supply rail and the amplifying circuit, a gate of the second transistor is coupled to the gate of the pass device, and a drain of the second transistor is coupled directly to the amplifying circuit.

2. The voltage regulator of claim 1 , wherein the first transistor comprises a p-type field effect transistor (PFET) having a source coupled to the supply rail.

3. The voltage regulator of claim 1 , further comprising a voltage bias circuit coupled to the gate of the first transistor.

4. The voltage regulator of claim 1 , wherein the amplifying circuit comprises:

an amplifier having the first input configured to receive the reference voltage, the second input coupled to the output of the voltage regulator via the feedback path, and the output; and

a buffer having an input coupled to the output of the amplifier, and an output coupled to the gate of the pass device.

5. The voltage regulator of claim 4 , wherein the first current source further comprises:

a third transistor coupled between the supply rail and the buffer, wherein the capacitor is coupled between a gate of the third transistor and the output of the voltage regulator.

6. The voltage regulator of claim 5 , wherein:

the first transistor comprises a first p-type field effect transistor (PFET) having a source coupled to the supply rail and a drain coupled to the amplifier; and

the third transistor comprises a second PFET having a source coupled to the supply rail and a drain coupled to the buffer.

7. The voltage regulator of claim 5 , further comprising a voltage bias circuit coupled to the gate of the first transistor and the gate of the third transistor.

8. The voltage regulator of claim 5 , wherein the second current source further comprises:

a fourth transistor coupled between the supply rail and the buffer, wherein a gate of the fourth transistor is coupled to the gate of the pass device.

9. The voltage regulator of claim 4 , wherein the amplifier comprises a cascode amplifier.

10. The voltage regulator of claim 4 , further comprising a bias generation circuit, wherein the bias generation circuit includes:

a resistor coupled between a first node and a second node, wherein the first node is coupled to a bias input of the amplifier;

a capacitor coupled between the first node and the second node; and

a bias transistor having a drain coupled to the second node, a gate coupled to the drain, and a source coupled to a ground.

11. The voltage regulator of claim 4 , wherein the buffer comprises a source follower.

12. A chip, comprising:

a pad;

a supply rail coupled to the pad;

a reference circuit configured to generate a reference voltage; and

the voltage regulator of claim 1 .

13. A method of operating a voltage regulator, wherein the voltage regulator includes a pass device coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplifying circuit coupled to a gate of the pass device, the method comprising:

detecting a transient voltage drop at the output of the voltage regulator via a capacitor;

increasing a bias current to the amplifying circuit based on the detected transient voltage drop;

detecting a gate voltage of the pass device; and

adjusting the bias current to the amplifying circuit based on the detected gate voltage, wherein:

the voltage regulator includes a first transistor coupled between a supply rail and the amplifying circuit, wherein a drain of the first transistor is directly coupled to the amplifying circuit;

increasing the bias current to the amplifying circuit based on the transient voltage drop comprises capacitively coupling the transient voltage drop to a gate of the first transistor via the capacitor, wherein:

the voltage regulator includes a second transistor coupled between the supply rail and the amplifying circuit, wherein a drain of the second transistor is directly coupled to the amplifying circuit, and a gate of the second transistor is coupled to the gate of the pass device; and

adjusting the bias current to the amplifying circuit based on the detected gate voltage comprises coupling a gate of the second transistor to the gate of the pass device.

14. The method of claim 13 , further comprising:

increasing the bias current to the amplifying circuit based on the transient voltage drop comprises capacitively coupling the transient voltage drop to a gate of the first transistor via the capacitor.

15. The method of claim 14 , wherein the transistor comprises a first p-type field effect transistor (PFET).