Charge/discharge control circuit and battery device
Provided is a technology capable of protecting a charge/discharge control circuit and a battery device from a reverse connection state without a separately provided protection circuit. The charge/discharge control circuit to be contained in a battery device including a secondary cell, an external positive terminal and an external negative terminal, and FETs which control charging and discharging of the secondary cell, respectively, includes: VDD and VSS terminals; a charge control terminal; a discharge control terminal; a voltage detection terminal to which a voltage applied to the external positive terminal is supplied; an NMOS transistor communicates the discharge control terminal and the voltage detection terminal; and a bipolar transistor having a collector to be connected to a drain of the NMOS transistor, an emitter to be connected to a source of the NMOS transistor, and a base to be connected to a bulk of the NMOS transistor and the VSS terminal.
1. A charge/discharge control circuit to be contained in a battery device including:
a secondary cell;
an external positive terminal and an external negative terminal to which a load, a positive pole of a charger, and a negative pole of the charger are connectable;
a charge control FET configured to control charging of the secondary cell; and
a discharge control FET configured to control discharging of the secondary cell,
the charge/discharge control circuit comprising:
a first power supply voltage input terminal to which, out of a first power supply voltage and a second power supply voltage, the first power supply voltage is supplied, the first power supply voltage and the second power supply voltage being generated by the secondary cell;
a second power supply voltage input terminal to which the second power supply voltage lower than the first power supply voltage is supplied;
a charge control terminal connected to a gate of the charge control FET;
a discharge control terminal connected to a gate of the discharge control FET;
a voltage detection terminal to which a voltage applied to the external positive terminal is supplied;
an NMOS transistor configured to communicate the discharge control terminal and the voltage detection terminal; and
a bipolar transistor having a collector connected to a drain of the NMOS transistor, an emitter connected to a source of the NMOS transistor, and a base connected to a bulk of the NMOS transistor and the second power supply voltage input terminal.
2. The charge/discharge control circuit according to claim 1 , further comprising PMOS transistors configured to communicate the discharge control terminal and the voltage detection terminal through a path different from a path communicated by the NMOS transistors.
3. The charge/discharge control circuit according to claim 1 , further comprising a booster circuit having an output terminal from which a voltage higher than the first power supply voltage is output,
wherein the NMOS transistor includes a gate connected to the output terminal of the booster circuit.
4. The charge/discharge control circuit according to claim 1 , wherein the NMOS transistor and the bipolar transistor are formed of an NMOS transistor including a parasitic bipolar transistor.
5. The charge/discharge control circuit according to claim 2 , wherein the NMOS transistor and the bipolar transistor are formed of an NMOS transistor including a parasitic bipolar transistor.
6. The charge/discharge control circuit according to claim 3 , wherein the NMOS transistor and the bipolar transistor are formed of an NMOS transistor including a parasitic bipolar transistor.
7. The charge/discharge control circuit according to claim 1 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
8. The charge/discharge control circuit according to claim 2 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
9. The charge/discharge control circuit according to claim 3 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
10. The charge/discharge control circuit according to claim 4 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
11. The charge/discharge control circuit according to claim 5 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
12. The charge/discharge control circuit according to claim 6 , wherein the charge/discharge control circuit is formed on a single semiconductor substrate.
13. A battery device comprising:
the charge/discharge control circuit of claim 1 ;
a secondary cell;
an external negative terminal;
an external positive terminal; and
a charge control FET and a discharge control FET which are connected between a positive pole of the secondary cell and the external positive terminal.