Adaptive on-time DC-to-DC buck regulators with constant switching frequency

1. A voltage regulator circuit comprising:

a first switch coupled to a power input;

a second switch coupled to the first switch;

a switching node between the first switch and the second switch;

an inductor coupled between the switching node and an output node;

a capacitor coupled between the output node and ground;

a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal;

a PWM circuit configured to generate the PWM signal based on at least an error signal; and

a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal;

wherein the phase detector comprises:

a first D flip-flop having a logic “1” as a D input, a reference clock signal as a clock input, and a reset signal as a reset input;

a second D flip-flop having a logic “1” as a D input, the PWM signal as a clock input, and the reset signal as a reset input; and

an AND gate, wherein Q outputs of the first and second D flip-flops are inputs to the AND gate, wherein the reset signal is an output of the AND gate;

wherein the error signal comprises the Q outputs of the first D flip-flop and the second D flip-flop;

wherein an adjustable current source increases a magnitude of an adjustable current responsive to the Q output of the first D flip-flop being a logic “1”; and

wherein the adjustable current source decreases the magnitude of the adjustable current responsive to the Q output of the second D flip-flop being a logic “1”.

2. The circuit of claim 1 , wherein the PWM circuit comprises:

a feedback circuit configured to initiate on-times of the PWM signal based on a voltage at the switching node and a voltage at the output node; and

an adaptive on-time circuit configured to terminate the on-times of the PWM signal based on the voltage at the output node and the error signal.

3. The circuit of claim 2 , wherein the adaptive on-time circuit comprises:

an adjustable current source configured to provide an adjustable current having a magnitude based on the error signal;

a capacitor coupled to the current source; and

a comparator configured to terminate the on-times of the PWM signal based on the voltage at the output node and a voltage across the capacitor.

4. The circuit of claim 3 , wherein:

the adjustable current source is further configured to increase the magnitude of the adjustable current responsive to a pulse of the reference clock signal occurring before a corresponding pulse of the PWM signal; and

the adjustable current source is further configured to decrease the magnitude of the adjustable current responsive to a pulse of the reference clock signal occurring after a corresponding pulse of the PWM signal.

5. The circuit of claim 4 , wherein the adaptive on-time circuit further comprises:

a fixed current source coupled to the capacitor, wherein the fixed current source is configured to provide a fixed current having a fixed magnitude;

wherein the adjustable current source is configured to increase the magnitude of the adjustable current by a fixed percentage of the fixed magnitude; and

wherein the adjustable current source is configured to decrease the magnitude of the adjustable current by the fixed percentage of the fixed magnitude.

6. The circuit of claim 5 , wherein:

the fixed percentage is approximately 15%.

7. The circuit of claim 2 , wherein the adaptive on-time circuit further comprises:

a control circuit configured to charge the capacitor when the on-times of the PWM signal begin.

8. The circuit of claim 7 , wherein the control circuit comprises:

a switch configured to discharge the capacitor when the switch is closed; and

an inverter configured to close the switch when the on-times of the PWM signal end.

9. The circuit of claim 2 , wherein the feedback circuit comprises:

a ramp generator configured to generate voltage ramps based on voltages across the inductor; and

a comparator circuit configured to initiate the on-times of the PWM signal based on the voltage ramps and the voltage at the output node.

10. A voltage regulator circuit comprising:

a first switch coupled to a power input;

a second switch coupled to the first switch;

a switching node between the first switch and the second switch;

an inductor coupled between the switching node and an output node;

a capacitor coupled between the output node and ground;

a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal;

a PWM circuit configured to generate the PWM signal based on at least an error signal; and

a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal;

wherein the phase detector comprises:

a divide-by-two circuit configured to divide-by-two the PWM signal and the reference clock signal; and

an exclusive-or gate, wherein the divided-by-two PWM signal and the divided-by-two reference clock signal are inputs to the exclusive-or gate, and wherein the error signal is an output of the exclusive-or gate.

11. The circuit of claim 10 , wherein the PWM circuit comprises:

a feedback circuit configured to initiate on-times of the PWM signal based on a voltage at the switching node and a voltage at the output node; and

an adaptive on-time circuit configured to terminate the on-times of the PWM signal based on the voltage at the output node and the error signal.

12. The circuit of claim 11 , wherein the adaptive on-time circuit comprises:

an adjustable current source configured to provide an adjustable current having a magnitude based on the error signal;

a capacitor coupled to the current source; and

a comparator configured to terminate the on-times of the PWM signal based on the voltage at the output node and a voltage across the capacitor.

13. A method for voltage regulation in a voltage regulator comprising a first switch coupled to a power input, a second switch coupled to the first switch, a switching node between the first switch and the second switch, and an inductor coupled between the switching node and an output node, the method comprising:

operating the first and second switches according to a pulse-width-modulated (PWM) signal;

generating the PWM signal based on at least an error signal;

generating the error signal based on a phase difference between the PWM signal and a clock reference signal;

providing an adjustable current to a capacitor, the adjustable current having a magnitude based on the error signal; and

terminating the on-times of the PWM signal based on the voltage at the output node and a voltage across the capacitor.

14. The method of claim 13 , further comprising:

initiating the on-times of the PWM signal based on a voltage at the switching node and a voltage at the output node; and

terminating the on-times of the PWM signal based on the voltage at the output node and the error signal.

15. The method of claim 13 , further comprising:

discharging the capacitor when the on-times of the PWM signal end.

16. The method of claim 15 , further comprising:

charging the capacitor when the on-times of the PWM signal begin.

17. The method of claim 13 , further comprising:

increasing the magnitude of the adjustable current responsive to a pulse of the reference clock signal occurring before a corresponding pulse of the PWM signal; and

decreasing the magnitude of the adjustable current responsive to a pulse of the reference clock signal occurring after a corresponding pulse of the PWM signal.

18. The method of claim 17 , further comprising:

providing a fixed current to the capacitor, the fixed current having a fixed magnitude;

increasing the magnitude of the adjustable current by a fixed percentage of the fixed magnitude; and

decreasing the magnitude of the adjustable current by the fixed percentage of the fixed magnitude.

19. The method of claim 18 , wherein:

the fixed percentage is approximately 15%.

20. The method of claim 13 , further comprising:

generating voltage ramps based on voltages across the inductor; and

initiating the on-times of the PWM signal based on the voltage ramps and the voltage at the output node.