IP Library Granted Patent US 11,482,976
Granted Patent B2
US 11,482,976 · App. 17/160,755 · Granted Oct 25, 2022

Differential amplifier

Inventor: Yoshiomi Shiina (Tokyo, JP)
Assignee: ABLIC INC.
H03F3/45183H03F2203/45026H03F2203/45508
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,482,976
App. No.
17/160,755
Granted
Oct 25, 2022
Kind
B2
Abstract

A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.

Claims (16)

1. A differential amplifier comprising:

first and second MOS transistors of a first conductivity type which constitute a differential input circuit;

a bias current source configured to supply a bias current to the first and second MOS transistors; and

a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and configured to limit a back-gate voltage of the first and second MOS transistors,

wherein the third MOS transistor has a gate directly connected to a gate of one of the first and second MOS transistors.

2. The differential amplifier according to claim 1 , wherein the third MOS transistor has a gate-source voltage higher than gate-source voltages of the first and second MOS transistors.

3. A differential amplifier comprising:

first and second MOS transistors of a first conductivity type which constitute a differential input circuit;

a bias current source configured to supply a bias current to the first and second MOS transistors;

a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and configured to limit a back-gate voltage of the first and second MOS transistors; and

a constant voltage source directly connected to a gate of the third MOS transistor and configured to supply the gate of the third MOS transistor wherein the third MOS transistor has a gate supplied with a bias voltage higher than voltages applied to input terminals of the differential input circuit.

4. The differential amplifier according to claim 3 , wherein a back-gate of the third MOS transistor is directly connected to a source of the third MOS transistor.

5. The differential amplifier according to claim 4 , wherein the third MOS transistor is a PMOS transistor.

6. The differential amplifier according to claim 1 , wherein a back-gate of the third MOS transistor is directly connected to a source of the third MOS transistor.

7. The differential amplifier according to claim 6 , wherein the third MOS transistor is a PMOS transistor.

8. The differential amplifier according to claim 1 , wherein a gate length of the third MOS transistor is larger than a gate length of each of the first and second MOS transistors.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2021
From: SHIINA, YOSHIOMI
To: ABLIC INC.
Reel/Frame 055064/0308 →
Priority Claims (1)
JP JP2020-019244 · Feb 7, 2020 · national
Continuity (1)
Related Publication 20210250005A1 · Aug 12, 2021