Memory system and method for operating memory controller included therein
A memory system may include: one or more memory devices each including a plurality of memory cells for storing data; a memory for storing meta data associated with the stored data; and a memory controller in communication with the memory and the one or more memory devices and for loading the meta data from the memory, and generating first meta page based on the meta data according to a first layout, and storing the first meta page in the memory device.
1. A memory system comprising:
one or more memory devices each including a plurality of memory cells for storing data;
a memory configured to store meta data associated with the stored data; and
a memory controller in communication with the memory and the one or more memory devices and configured to load the meta data from the memory, and generate a first meta page based on the meta data according to a first layout, and store the first meta page in the memory device,
wherein the memory controller is further configured to receive a request from a host and generate a second meta page based on a second layout different from the first layout in response to the request from the host.
2. The memory system of claim 1 , wherein the request includes at least one of a shutdown request, a firmware update request, a format request, and a sanitization request.
3. The memory system of claim 1 , wherein the memory controller is further configured to divide the meta data into multiple meta slices and the first meta page includes a single meta slice among the multiple meta slices.
4. The memory system of claim 3 , wherein the first meta page further includes journal data indicating a change in the meta data.
5. The memory system of claim 1 , wherein the memory controller is further configured to divide the meta data into multiple meta slices and the second meta page includes at least portions of two meta slices.
6. The memory system of claim 1 , wherein a plurality of memory devices are connected to the memory controller respectively through channels that are independent from each other, and
wherein at least one of the first meta page and the second meta page is stored in a super page including respective pages of the plurality of memory devices.
7. The memory system of claim 6 , wherein at least one of the first meta page and the second meta page has a size corresponding to that of the super page.
8. The memory system of claim 1 , wherein each of the first meta page and the second meta page includes a field indicating information about which layout is used.
9. The memory system of claim 8 , wherein the memory controller is further configured to read a certain meta page stored in the memory device, determine a layout of the certain meta page based on the field included in the certain meta page, and extract data from the certain meta page based on the layout determined.
10. The memory system of claim 1 , wherein each of the first meta page and the second meta page further includes parity data having a fixed size and used to recover an error of the meta data.
11. A method for operating a memory controller, the method comprising:
receiving a request from a host in communication with the memory controller storing a first meta page generated during a runtime operation based on a first layout;
reading meta data stored in a memory in response to the request;
obtaining at least one meta slice by dividing the meta data;
generating a second meta page including the at least one meta slice based on a second layout different from the first layout; and
storing the second meta page in at least one memory device in communication with the memory controller.
12. The method of claim 11 , wherein the request includes at least one of a shutdown request, a firmware update request, a format request, and the sanitization request.
13. The method of claim 11 , wherein the first meta page includes a single meta slice.
14. The method of claim 11 , wherein the first meta page includes journal data indicating a change in the meta data.
15. The method of claim 11 , wherein the second meta page includes at least portions of two metal slices.
16. The method of claim 15 , wherein each of the first meta page and the second meta page includes a field indicating information about which layout is used.
17. The method of claim 16 , further comprising, after the storing:
reading a certain meta page stored in the at least one memory device;
determining a layout of the certain meta page based on the field included in the certain meta page; and
extracting data from the certain meta page based on the layout determined.
18. The method of claim 11 , wherein a plurality of memory devices are connected to the memory controller respectively through channels that are independent from each other, and
wherein the storing includes storing the second meta page in a super page including respective pages of the plurality of memory devices.
19. The method of claim 18 , wherein the second meta page has a size corresponding to that of the super page.
20. The method of claim 11 , wherein each of the first meta page and the second meta page includes parity data having a fixed size and used to recover an error of the meta data.