Time synchronisation

1. An integrated circuit comprising:

a timing synchronisation unit comprising a hardware timer;

a non-Ethernet network interface configured to communicate with another integrated circuit having another hardware timer; and

a processor,

wherein:

the timing synchronisation unit is configured, in response to receiving a timing trigger generated at time t 1 from the other integrated circuit via a wired link, to capture a local time t 2 using the hardware timer and provide the local time t 2 to the processor;

the timing synchronisation unit is configured to, in response to receiving the timing trigger, generate an interrupt;

the processor is configured to receive the interrupt and, in response to receiving the interrupt, read the other hardware timer via the non-Ethernet network interface to obtain a remote time t 1 ′; and

the processor is configured to compute a timing offset between a remote time obtained from the remote time t 1 ′ read from the other hardware timer via the non-Ethernet network interface and the local time t 2 for time synchronisation.

2. The integrated circuit of claim 1 ,

wherein the non-Ethernet network interface comprises a peripheral component interconnect express (PCIe) interface.

3. The integrated circuit of claim 1 , further comprising:

a time-sensitive networking Ethernet network interface.

4. The integrated circuit of claim 3 ,

wherein the time-sensitive networking Ethernet network interface complies with IEEE 802.1AS.

5. The integrated circuit of claim 3 ,

wherein the time-sensitive networking Ethernet network interface complies with IEEE 802.1Q-2018 or IEEE 1588.

6. The integrated circuit of claim 1 ,

wherein each of the hardware timer and the other hardware timer is a Precision Time Protocol (PTP) timer or a generalised Precision Time Protocol (gPTP) timer.

7. The integrated circuit of claim 1 ,

wherein the timing trigger is generated cyclically, on demand and/or in response to an event.

8. The integrated circuit of claim 1 ,

wherein the processor is configured to cause a change in operation of the hardware timer in dependence on the timing offset.

9. The integrated circuit of claim 1 , further comprising:

a pin for receiving the timing trigger; and

a path for transmitting the timing trigger from the pin to the timing synchronisation unit.

10. An integrated circuit comprising:

a time-sensitive networking Ethernet network interface;

a timing synchronisation unit comprising a hardware timer; and

a non-Ethernet network interface configured to communicate with another integrated circuit having another hardware timer,

wherein:

the timing synchronization unit is configured to generate a timing trigger at time t 1 and to transmit the timing trigger to the other integrated circuit via a wired link such that the other integrated circuit, in response to receiving the timing trigger, captures a local time t 2 using the other hardware timer, provides the local time t 2 to a processor, and generate an interrupt;

the timing synchronisation unit is configured to, in response to the interrupt, provide a remote time t 1 ′ to the processor via the non-Ethernet network interface for the processor to compute a timing offset between a remote time obtained from the remote time t 1 ′ via the non-Ethernet network interface and the local time t 2 for time synchronisation.

11. The integrated circuit of claim 10 ,

wherein the non-Ethernet network interface comprises a selector for selecting between the time from the hardware timer and another internal timer in the non-Ethernet network interface.