Control circuits with peak current limit protection for switched mode power supplies

1. An electronic circuit for limiting current in a switching power converter comprising: a first comparator configured to: perform a first comparison to compare a first current reference signal with a signal representing an input current; and generate a first current error signal based on the first comparison; a second comparator configured to: perform a second comparison to compare a second current reference signal with the signal representing the input current; and generate a second current error signal based on the second comparison; and a first summer configured to adjust a first summer input error signal based on a second summer input error signal; wherein the first summer input error signal is based on the first current error signal; and wherein the second summer input error signal is based on the second current error signal.

2. The electronic circuit of claim 1 further comprising:

a first amplifier configured to adjust the first current error signal based on an integrator coefficient; and

a third comparator configured to:

perform a third comparison to compare the second current error signal with a previous value of the first current error signal adjusted based on the integrator coefficient; and

modify the second current error signal based on the third comparison.

3. The electronic circuit of claim 2 further comprising a second summer configured to generate an integrator value via addition of the modified second current error signal with the first current error signal adjusted based on the integrator coefficient.

4. The electronic circuit of claim 3 , wherein the second summer input error signal is further based on the integrator value.

5. The electronic circuit of claim 2 further comprising a second amplifier configured to adjust the first current error signal based on a proportional gain coefficient.

6. The electronic circuit of claim 5 , wherein the first summer input error signal is further based on the first current error signal adjusted based on the proportional gain coefficient.

7. The electronic circuit of claim 2 , wherein the third comparator is configured to modify the second current error signal based on the signal representing the input current being greater than the second current reference signal.

8. The electronic circuit of claim 1 further comprising a control signal generator configured to generate one or more control signals for controlling at least one power switch based on an output of the first summer.

9. The electronic circuit of claim 1 , wherein the second comparator is configured to generate the second current error signal based on a difference between the signal representing the input current and the second current reference signal.

10. The electronic circuit of claim 1 further comprising a third comparator configured to:

perform a third comparison to compare a third current reference signal with the signal representing the input current; and

generate a signal based on the third comparison.

11. The electronic circuit of claim 10 further comprising a power switch;

wherein the electronic circuit is configured to turn off the power switch for a defined period of time if the signal representing the input current is greater than the third current reference signal.

12. The electronic circuit of claim 10 , wherein the third current reference signal is greater than the second current reference signal.

13. A method for limiting current in a switching power converter, the method comprising:

performing, via a first comparator, a first comparison to compare a first current reference signal with a signal representing an input current;

generating a first current error signal based on the first comparison;

performing, via a second comparator, a second comparison to compare a second current reference signal with the signal representing the input current;

generating a second current error signal based on the second comparison; and

adjusting, via a first summer, a first summer input error signal based on a second summer input error signal;

wherein the first summer input error signal is based on the first current error signal; and

wherein the second summer input error signal is based on the second current error signal.

14. The method of claim 13 further comprising:

adjusting, via a first amplifier, the first current error signal based on an integrator coefficient; and

performing, via a third comparator, a third comparison to compare the second current error signal with a previous value of the first current error signal adjusted based on the integrator coefficient; and

modify the second current error signal based on the third comparison.

15. The method of claim 14 further comprising generating, via a second summer, an integrator value via addition of the modified second current error signal with the first current error signal adjusted based on the integrator coefficient.

16. The method of claim 15 , wherein the second summer input error signal is further based on the integrator value.

17. The method of claim 14 further comprising adjusting, via a second amplifier, the first current error signal based on a proportional gain coefficient.

18. The method of claim 17 , wherein the first summer input error signal is further based on the first current error signal adjusted based on the proportional gain coefficient.

19. The method of claim 13 further comprising:

performing, via a third comparator, a third comparison to compare a third current reference signal with the signal representing the input current; and

generating a signal based on the third comparison.

20. The method of claim 19 further comprising turning off a power switch for a defined period of time if the signal representing the input current is greater than the third current reference signal.