Image sensor

1. An image sensor, comprising:

a substrate having a first surface and a second surface that are opposite to each other, the substrate including a plurality of unit pixel regions having photoelectric conversion regions and floating diffusion regions disposed adjacent to the first surface,

gate electrodes disposed on the first surface of the substrate,

a pixel isolation pattern disposed in the substrate and configured to define the plurality of unit pixel regions; and

an interconnection layer disposed on the first surface of the substrate, the interconnection layer includes a conductive structure,

wherein the conductive structure comprises:

a connection portion that extends parallel to the first surface of the substrate and is spaced apart from the first surface of the substrate, a bottom surface of the connection portion is co-planar with top surfaces of the gate electrodes; and

contacts that extend vertically from the connection portion towards the first surface of the substrate, and

wherein each of the contacts are spaced apart from each other with the pixel isolation pattern interposed therebetween, wherein each of the contacts are coupled to the floating diffusion regions, respectively.

2. The image sensor of claim 1 , wherein:

the interconnection layer further comprises interconnection lines and vias disposed on a top surface of the conductive structure; and

the interconnection lines and the vias are configured to be electrically connected to the conductive structure and the interconnection lines and the vias include a material that is different from the conductive structure.

3. The image sensor of claim 1 , wherein:

the substrate comprises a plurality of pixel groups, each of the plurality of pixel groups includes a plurality of the unit pixel regions;

the floating diffusion regions are disposed in at least one of the plurality of pixel groups,

the contacts are disposed on the floating diffusion regions, respectively, and

the connection portion extends to connect to the contacts.

4. The image sensor of claim 1 ,

wherein the interconnection layer further comprises:

interconnection lines that contact the conductive structure;

a first insulating layer disposed between the interconnection lines and the first surface of the substrate, the first insulating layer is arranged to cover the gate electrodes and the first surface of the substrate; and

the conductive structure penetrates the first insulating layer and is configured to electrically connect the floating diffusion regions to the interconnection lines.

5. The image sensor of claim 1 ,

wherein the connection portion contacts top surfaces of a partial portion of the gate electrodes.

6. The image sensor of claim 1 , wherein:

the conductive structure has a first height extending vertically from the first surface of the substrate to a top surface of the conductive structure; and

the first height of the conductive structure is in a range of about 50 nm to about 400 nm.

7. The image sensor of claim 1 , wherein:

the interconnection layer further includes an auxiliary conductive pattern; and

a top surface of the auxiliary conductive pattern is disposed at a same level as a top surface of the connection portion.

8. The image sensor of claim 7 , further comprising:

the gate electrodes include a first gate electrode and a second gate electrode that are spaced apart from each other with the pixel isolation pattern interposed therebetween; and

the auxiliary conductive pattern crosses the pixel isolation pattern and is configured to connect the first gate electrode to the second gate electrode.

9. An image sensor, comprising:

a substrate having a first surface and a second surface that are opposite to each other, the substrate including a plurality of pixel groups, each of the plurality of pixel groups including first to fourth unit pixel regions, the first to fourth unit pixel regions having first to fourth floating diffusion regions, respectively;

a pixel isolation pattern penetrating the substrate and configured to define the first to fourth unit pixel regions;

gate electrodes disposed on the first surface of the substrate;

color filters and micro lenses disposed on the second surface of the substrate; and

an interconnection layer disposed on the first surface of the substrate, the interconnection layer includes a conductive structure,

wherein the conductive structure comprises:

a connection portion that extends parallel to the first surface of the substrate and is spaced apart from the first surface of the substrate, a bottom surface of the connection portion is co-planar with top surfaces of the gate electrodes;

first to fourth contacts that extend vertically from the connection portion and are coupled to the first to fourth floating diffusion regions, respectively; and

the connection portion is configured to electrically connect the first to fourth contacts to each other.

10. The image sensor of claim 9 , wherein:

the interconnection layer further comprises interconnection lines that contact the conductive structure,

wherein the conductive structure includes tungsten, and

the interconnection lines includes copper.

11. The image sensor of claim 10 , wherein:

the interconnection layer further includes a first insulating layer that is arranged to cover the first surface of the substrate;

the interconnection lines are disposed on the first insulating layer; and

the conductive structure penetrates the first insulating layer and is disposed between the interconnection lines and the first surface of the substrate.

12. The image sensor of claim 9 , wherein the pixel isolation pattern includes poly silicon.

13. The image sensor of claim 9 , wherein:

the interconnection layer further includes an auxiliary conductive pattern; and

the auxiliary conductive pattern extends parallel to a portion of the connection portion and is spaced apart from the portion of the connection portion.

14. The image sensor of claim 13 , further comprising:

the gate electrodes include first to fourth gate electrodes disposed on the first surface of the substrate and are disposed in the first to fourth unit pixel regions, respectively,

the first and second gate electrodes are arranged to be symmetric to each other with the pixel isolation pattern interposed therebetween; and

the auxiliary conductive pattern extends from a top surface of the first gate electrode to a top surface of the second gate electrode in a direction parallel to the first surface of the substrate.

15. The image sensor of claim 9 , wherein:

the interconnection layer further comprises a pair of auxiliary conductive patterns that are spaced apart from each other;

the pair of auxiliary conductive patterns have top surfaces that are disposed at a same level as a top surface of the conductive structure; and

the conductive structure is disposed between the pair of auxiliary conductive patterns.

16. An image sensor, comprising:

a substrate having a first surface and a second surface that are opposite to each other, the substrate including a pixel array region, an optical black region, and a pad region, the pixel array region including a plurality of unit pixel regions having photoelectric conversion regions,

a pixel isolation pattern and a device isolation pattern disposed in the substrate, the pixel isolation pattern penetrates the device isolation pattern and is configured to define the plurality of unit pixel regions;

an interconnection layer disposed on the first surface of the substrate;

transfer transistors and logic transistors disposed on the first surface of the substrate and including gate electrodes;

color filters and micro lenses disposed on the second surface of the substrate;

a first light-blocking pattern and a first pad terminal disposed in the optical black region of the substrate, the first light-blocking pattern penetrates the substrate, the first pad terminal is disposed on the second surface of the substrate and is configured to be electrically connected to the first light-blocking pattern; and

a second pad terminal disposed in the pad region of the substrate and disposed on the second surface of the substrate,

wherein the interconnection layer comprises:

a first insulating layer arranged to cover the first surface of the substrate;

a conductive structure penetrating the first insulating layer, the conductive structure including a connection portion that extends parallel to the first surface of the substrate, and contacts that extend vertically from the connection portion towards the first surface of the substrate, wherein a bottom surface of the connection portion is co-planar with top surfaces of the gate electrodes; and

interconnection lines and vias disposed on and coupled to the conductive structure.

17. The image sensor of claim 16 , wherein:

the pixel isolation pattern includes a first isolation pattern arranged to cover an inner surface of a first trench of the substrate, and a second isolation pattern that fills the first trench;

the second isolation pattern includes poly silicon doped with impurities; and

the second isolation pattern is configured to receive a negative bias voltage through the first pad terminal.