FinFETs with low source/drain contact resistance
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
1. A semiconductor device comprising:
a gate structure on a substrate;
a source/drain on each of opposite sides of the gate structure and on the substrate, each source/drain including a faceted region and a columnar region below the faceted region;
a source/drain contact on each of the source/drains, wherein each of the source/drain contacts wraps around the sides of one source/drain;
an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts; and
wherein a portion of each source/drain contact has an outer shape that matches the outer shape on both sides of the underlying source/drain, and a portion of each source/drain contact extends along a sidewall of the columnar region.
2. The semiconductor device of claim 1 , wherein the source/drain contacts are formed of a material comprising titanium, tungsten, aluminum, copper, or tantalum.
3. The semiconductor device of claim 1 , wherein the source/drain contacts are in contact with respective portions of the substrate on opposite sides of the respective source/drains.
4. The semiconductor device of claim 1 , wherein the gate structure further includes a gate sidewall spacer.
5. The semiconductor device of claim 4 , wherein a portion of the ILD layer extends between the source/drain contact and the sidewall spacer.
6. The semiconductor device of claim 1 , further comprising at least one channel layer between the source/drains, wherein each of the source/drains is in physical and electrical contact with the at least one channel layer.
7. The semiconductor device of claim 1 , wherein respective outer surfaces of each source/drain contact are in physical contact with the ILD.
8. A semiconductor device; comprising:
a gate structure on a fin, wherein the gate structure includes a gate sidewall spacer;
wherein the fin includes respective source/drain regions on opposite sides of the gate structure;
respective source/drain extensions extending above the fin in the respective source/drain regions, each source/drain extension including a faceted upper region and a columnar lower region;
a source/drain contact, wherein the source/drain contact wraps around the sides of a respective source/drain extension and extends along sidewalls of the respective faceted upper region and the columnar lower region of the respective source/drain extension;
an interlayer dielectric (ILD) layer on opposite sides of each of the source/drain contacts;
at least one channel layer between the source/drains, wherein each of the source/drains is in physical and electrical contact with the at least one channel layer.
9. The semiconductor device of claim 8 , wherein the source/drain contacts are formed of a material comprising titanium, tungsten, aluminum, copper, or tantalum.
10. The semiconductor device of claim 8 , wherein the source/drains respectively have a diamond shaped profile.
11. The semiconductor device of claim 8 , further comprising a liner between the source/drains and the source/drain contacts.
12. The semiconductor device of claim 8 , further comprising a dielectric material contacting outer surfaces of the source/drain contacts.
13. The semiconductor device of claim 8 , wherein the respective source/drains having upper facets extending away from a center point and lower facets extending toward a center point, when proceeding from top to bottom.
14. The semiconductor device of claim 13 , wherein the respective source/drain contacts contact the upper facets and the lower facets.
15. The semiconductor device of claim 8 , wherein the source/drain contact includes a silicide liner extending along sidewalls of the source/drains.
16. A semiconductor device, comprising:
a plurality of semiconductor fins;
an isolation layer, the isolation layer having a portion with a top surface that extends between the lowest portions of the respective semiconductor fins;
fin extensions formed on respective source and drain regions of the plurality of semiconductor fins that extend vertically and laterally beyond boundaries of the plurality of semiconductor fins, wherein respective fin extensions further extend lower than the top surface of the portion of the isolation layer;
conductive contacts formed in contact with a top surface, an underside, and sidewalls of the respective fin extensions; and
a conductive liner directly between the fin extensions and the conductive contacts.
17. The semiconductor device of claim 16 , wherein the conductive liner is a silicide layer.
18. The semiconductor device of claim 16 , wherein the conductive liner contacts the portion of the isolation layer.
19. The semiconductor device of claim 16 , wherein the respective fin extensions include an upper faceted portion and a lower columnar portion.
20. The semiconductor device of claim 19 , wherein respective conductive contacts extend along sidewalls of respective lower columnar portions.