Instruction error handling

1. An apparatus, comprising:

an instruction storage circuit that includes: an instruction memory configured to store a plurality of instructions, wherein the instruction memory includes an error storage circuit;

a memory control circuit configured to: retrieve a particular instruction from the instruction memory; detect a data integrity error in the particular instruction; generate and store a corrected version of the particular instruction in the error storage circuit; and in response to receiving a subsequent request to retrieve the particular instruction, cause a response to the subsequent request to be provided from the error storage circuit, wherein the memory control circuit, in response to detecting that a different instruction has a data integrity error that is a multi-bit error, is further configured to: retrieve, from a higher-level memory, a cache line that includes the different instruction.

2. The apparatus of claim 1 , further comprising: an execution pipeline configured to execute instructions received from the instruction storage circuit; and a trap logic circuit configured, in response to detecting the data integrity error, to cause a flush of instructions from the execution pipeline and a refetch of a group of instructions that includes the subsequent request for the particular instruction.

3. The apparatus of claim 2 , wherein the memory control circuit, in response to the data integrity error being a single-bit error, is further configured to perform an ECC-correction operation on the particular instruction to generate the corrected version of the particular instruction for storage in the error storage circuit.

4. The apparatus of claim 3 , wherein the memory control circuit, in response to detecting that a different instruction has a data integrity error that is a multi-bit error, is further configured to: write the different instruction from the retrieved cache line to the error storage circuit; write the cache line to an instruction storage in the instruction memory; and wherein the memory control circuit, in response to a refetch of the different instruction, is further configured to: cause the different instruction to be provided to the execution pipeline from the error storage circuit; and check whether a version of the different instruction stored in the instruction storage matches a version of the different instruction stored in the error storage circuit.

5. The apparatus of claim 2 , wherein the memory control circuit is further configured to: store the corrected version of the particular instruction to a corresponding location in the instruction memory; in response to the subsequent request to retrieve the particular instruction: determine that a corrected version of the particular instruction has been stored in the error storage circuit; and provide the corrected version of the particular instruction from the error storage circuit to the execution pipeline.

6. The apparatus of claim 5 , wherein the memory control circuit is further configured, in response to the subsequent request to retrieve the particular instruction, to: retrieve the corrected version from the corresponding location in the instruction memory; and if the corrected version has a data integrity error, mark the corresponding location in the instruction memory as faulty.

7. The apparatus of claim 1 , wherein the instruction storage circuit includes multiple memory banks, and wherein the error storage circuit includes first and second error buffers; and wherein the memory control circuit is further configured, in response to the particular instruction spanning two of the multiple memory banks, to store the corrected version of the particular instruction using portions of the first and second error buffers.

8. The apparatus of claim 1 , wherein one or more error buffers in the error storage circuit are implemented using flip-flops, and wherein other memory cells in the instruction memory are implemented using SRAMs.

9. The apparatus of claim 1 , wherein the memory control circuit is further configured to track data integrity errors in instructions in the instruction storage circuit over time.

10. A method, comprising:

receiving, by a circuit of a computer processor executing a program, a particular instruction of the program, wherein the particular instruction is received from an instruction memory of the computer processor;

detecting, by the circuit, a data integrity error in the particular instruction; in response to the detecting, performing, by the circuit:

signaling for a flush of an execution pipeline of the computer processor and a refetch of a group of instructions that includes the particular instruction;

correcting, during a flush window associated with the flush, the data integrity error to generate a corrected version of the particular instruction; and

storing the corrected version in an error storage location within the instruction memory;

after the flush and during the refetch, re-receiving, by the circuit, the corrected version of the particular instruction from the error storage location; and

providing, by the circuit, the corrected version of the particular instruction to a stage of the execution pipeline, thus permitting forward progress of the program, wherein the circuit, in response to detecting that a different instruction has a data integrity error that is a multi-bit error, is further configured to: retrieve, from a higher-level memory, a cache line that includes the different instruction.

11. The method of claim 10 , further comprising: storing, by the circuit, an indication that the data integrity error is correctable by the circuit; and upon re-receiving the particular instruction, providing, based on the stored indication, the corrected version of the particular instruction from the error storage location to the stage of the execution pipeline.

12. The method of claim 10 , further comprising: determining, by the circuit, that a copy of the particular instruction reloaded into a storage location in the instruction memory still has the data integrity error; and in response to the determining, causing, by the circuit, the storage location to be marked as faulty.

13. The method of claim 10 , further comprising: in response to detecting, by the circuit, that a different instruction has a data integrity that is not correctable by the circuit: storing, by the circuit, an indication that the different instruction has a non-correctable data integrity error; and signaling that an instruction access fault should be issued for the different instruction, wherein the instruction access fault causes the different instruction to be fetched from a higher-level memory and loaded into the instruction memory for a subsequent access.

14. The method of claim 10 , wherein correction of data integrity errors in the program is suppressed upon detecting the data integrity error in the particular instruction, and wherein the method further comprises: after providing the corrected version of the particular instruction to the execution pipeline, clearing the error storage location, thus re-enabling detecting and correcting of data integrity errors in instructions fetched from the instruction memory.

15. An apparatus, comprising:

an instruction storage circuit that includes an instruction memory, wherein the instruction memory includes a redundant portion;

a trap logic unit; and

an execution pipeline;

wherein the instruction storage circuit is configured to: receive a request for a particular instruction; detect, in a storage location in the instruction memory, a data integrity error in the particular instruction; in response to detecting the data integrity error, signal the trap logic unit to cause a flush of instructions from the execution pipeline; generate, during a flush window associated with the flush, a corrected version of the particular instruction; store the corrected version in the redundant portion of the instruction memory; receive a re-request for the particular instruction during a refetch of a group of instructions from the instruction memory, wherein the refetch occurs after the flush; and in response to the re-request, provide, to the execution pipeline from the redundant portion of the instruction memory, the corrected version of the particular instruction, wherein the data integrity error is a single-bit error, and wherein the instruction storage circuit is further configured, in response to detecting a multi-bit error in a different instruction in the instruction memory, to: send an indication of the multi-bit error to the execution pipeline along with the different instruction without correcting the multi-bit error; and wherein the trap logic unit is configured to take an instruction access fault on the different instruction in response to receiving the indication of the multi-bit error, wherein the instruction access fault includes retrieving the different instruction from a higher-level memory.

16. The apparatus of claim 15 , wherein the instruction memory includes a plurality of memory banks, and wherein the redundant portion of the instruction memory includes at least one of the plurality of memory banks.

17. The apparatus of claim 16 , wherein the redundant portion includes two memory banks configured to store an instruction that straddles memory banks.

18. The apparatus of claim 15 , wherein the instruction storage circuit is further configured to also store the corrected version in a storage location of a non-redundant portion of the instruction memory; and wherein, in response to the re-request, the instruction storage circuit is further configured to compare the corrected version stored in the non-redundant and redundant portions of the instruction memory to determine if there is a persistent error in the non-redundant portion of the instruction memory.

19. The apparatus of claim 18 , wherein the instruction storage circuit, in response to determining there is a persistent error in the non-redundant portion of the instruction memory, is further configured to store an indication that a subsequent request to the storage location is to be remapped to a different storage location.