Forced debug mode entry

1. An apparatus comprising:

a processor including:

a logic circuit configured to receive a halt request, wherein responsive to receiving the halt request while the processor is not in a quiescent state, the logic circuit is further configured to, after a predetermined amount of time has elapsed from receiving the halt request, force the processor to halt operation by forcing the processor into a quiescent state, wherein a current state of the processor is accessible by a debug circuit in the processor when the processor is halted and in the quiescent state, wherein the logic circuit is further configured to force the processor into a quiescent state by resetting one or more bus interface units.

2. The apparatus of claim 1 , wherein the debug circuit is configured to generate the halt request responsive to receiving a command from a debugger external to the processor.

3. The apparatus of claim 1 , wherein the logic circuit is further configured to provide an acknowledgement signal to the debug circuit to indicate that the processor has been forced into a quiescent state, and wherein the debug circuit is configured to control operation of the processor responsive to receiving the acknowledgement signal.

4. The apparatus of claim 1 , wherein the logic circuit is further configured to force the processor into a quiescent state by canceling one or more pending transactions.

5. The apparatus of claim 1 , wherein the logic circuit includes a timer configured to track an amount of time that has elapsed up after receiving the halt request up to the predetermined amount of time, wherein the predetermined amount of time is programmable.

6. The apparatus of claim 1 , further comprising a status register, wherein responsive to forcing the processor into the quiescent state, the logic circuit is further configured to cause contents of the status register to be updated to indicate that the processor has been forced into the quiescent state.

7. The apparatus of claim 1 , wherein the logic circuit includes a timer, wherein responsive to the logic circuit receiving the halt request, the timer is configured to begin operation and further configured to generate an indication that the predetermined amount of time has elapsed.

8. The apparatus of claim 1 , wherein the current state of the processor includes contents of one or more registers internal to the processor.

9. The apparatus of claim 1 , wherein the processor further includes an execution pipeline having at least one execution unit, wherein the logic circuit is coupled to the at least one execution unit and is configured to retire instructions executed by the at least one execution unit.

10. A method comprising:

conveying, in a processor and in response to a command received from an external debugger, a halt request from a debug circuit to a retire logic circuit;

initiating operation of a timer in the retire logic circuit in response to receiving the halt request when the processor is not in a quiescent state;

in response to the timer indicating a predetermined time threshold has been reached, forcing the processor into the quiescent state; and

providing a halt acknowledgement to the debug circuit in response to receiving the halt request, wherein a current state of the processor is accessible by the debug circuit when the processor is halted and in the quiescent state, wherein forcing the processor into the quiescent state comprises the retire logic circuit canceling one or more pending transactions, wherein canceling the one or more pending transaction comprises resetting one or more bus interface units.

11. The method of claim 10 , wherein the current state of the processor includes contents of one or more registers internal to the processor, and wherein the method further comprises the debug circuit conveying the contents of the one or more registers to the external debugger.

12. The method of claim 10 , further comprising the debug circuit controlling operation of the processor responsive to receiving the halt acknowledgement, wherein controlling operation includes the debug circuit causing single-step execution of instructions in the processor.

13. The method of claim 10 , further comprising updating a status register to indicate that the processor is in the quiescent state.

14. The method of claim 10 , wherein the timer is a programmable timer, and wherein the method further comprises programming the timer with the predetermined time threshold.

15. A processor comprising:

a debug circuit coupled to a debug interface, wherein the debug circuit is configured to generate a request to halt operation of the processor responsive to receiving a command received, through the debug interface, from a debugger external to the processor; a timer configured to, if the processor is not in a quiescent state, begin tracking an amount of time elapsed from a time the request was generated; and a retire logic circuit configured to, responsive to the timer indicating that a time threshold has been reached, cause the processor to halt operation and enter the quiescent state and further configured to provide, to the debug circuit, an acknowledgement indicating that the processor is in the quiescent state, wherein the retire logic circuit is configured to force the processor into the quiescent state by canceling one or more pending transactions, wherein canceling one or more pending transactions includes the retire logic circuit resetting one or more bus interface circuits.

16. The processor of claim 15 , wherein the debug circuit is further configured to, subsequent to the retire logic circuit forcing the processor into the quiescent state, read contents stored in one or more processor registers and further configured to convey the contents to the external debugger.

17. The processor of claim 15 , wherein the debug circuit is further configured to, subsequent to the retire logic circuit forcing the processor into the quiescent state, cause stepwise execution of instructions by an execution unit in the processor.