IP Library Granted Patent US 11,581,306
Granted Patent B2
US 11,581,306 · App. 17/180,174 · Granted Feb 14, 2023

Monolithic single chip integrated radio frequency front end module configured with single crystal acoustic filter devices

Inventors: Shawn R. Gibb (Huntersville, NC); David Aichele (Huntersville, NC); Ramakrishna Vetury (Charlotte, NC); Mark D. Boomgarden (Huntersville, NC); Jeffrey B. Shealy (Davidson, NC)
Assignee: Akoustis, Inc.
H01L27/0605H01L21/0254H01L21/02598H01L21/8252H01L27/0617H01L27/20H01L29/2003H01L29/41766H01L29/80H03F3/19H03F3/21H03H3/08H03H9/46H04B1/44H01L21/0242H01L21/02378H01L21/02381H01L21/02389H01L23/66H01L29/7786H01L41/183H01L41/314H01L41/37H01L2223/6683H01L2224/48091H03F2200/165H03F2200/171H03F2200/294H03F2200/451H03H3/02H03H9/02007H03H9/0542H03H9/1014
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Quick Facts
Patent No.
US 11,581,306
App. No.
17/180,174
Granted
Feb 14, 2023
Kind
B2
Abstract

A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

Claims (36)

1. A monolithic single chip device, the device comprising:

a substrate having an underlying cavity region;

a first piezoelectric layer formed overlying the substrate;

a first device configured within the first piezoelectric layer and within the underlying cavity region;

one or more second piezoelectric layers formed overlying the first piezoelectric layer;

a second device configured within or overlying the one or more second piezoelectric layers; and

wherein the first piezoelectric layer and the one or more second piezoelectric layers are formed as a monolithic stack.

2. The device of claim 1 wherein the substrate comprises a silicon, a sapphire, a silicon carbide, a GaN bulk, a GaN template, an AlN bulk, an AlN template, or an Al x Ga 1-x N template material.

3. The device of claim 1 wherein the substrate comprises a silicon, a sapphire, a silicon carbide, a GaN bulk, a GaN template, an AlN bulk, an AlN template, or an Al x Ga 1-x N template material.

4. The device of claim 1 wherein at least one of the one or more second piezoelectric layers comprises an AlN, an AlGaN, a GaN, an InN, an InGaN, an AlInN, an AlInGaN, or a BN material.

5. The device of claim 1 wherein the first device comprises a passive device, a filter device, a switch device, an amplifier device, or an acoustic resonator device.

6. The device of claim 1 wherein the second device comprises a switch device, an antenna switch module, a filter device, an amplifier device, a low noise amplifier device, a power amplifier device, a power amplifier duplexer device, a passive device, or an active device.

7. The device of claim 1 further comprising a cap layer overlying the one or more second piezoelectric layers.

8. The device of claim 7 wherein the cap layer comprises a silicon, a sapphire, a silicon carbide, a GaN bulk, a GaN template, an AlN bulk, an AlN template, or an Al x Ga 1-x N template material.

9. The device of claim 7 wherein the second device is configured overlying the cap layer.

10. The device of claim 7 wherein the first piezoelectric layer is characterized by a thickness of about 0.01 um to about 10.0 um;

wherein at least one the one or more second piezoelectric layers is characterized by a thickness ranging from about 10 nm to about 1200 nm; and

wherein the cap layer is characterized by a thickness ranging from about 0.10 nm to about 5.0 nm.

11. A method for fabricating a monolithic single chip device, the method comprising:

providing a substrate having an underlying cavity region;

forming a first piezoelectric layer overlying the substrate;

processing the first single crystal piezoelectric layer to form a first device within the first piezoelectric layer and within the underlying cavity region;

forming one or more second piezoelectric layers overlying the first piezoelectric layer; and

processing at least one of the one or more second piezoelectric layers to form a second device;

wherein the first piezoelectric layer and the one or more second piezoelectric layers form a monolithic stack.

12. The method of claim 11 wherein the substrate comprises a silicon, a sapphire, a silicon carbide, a GaN bulk, a GaN template, an AlN bulk, an AlN template, or an Al x Ga 1-x N template material.

13. The method of claim 11 wherein the first piezoelectric layer comprises an AlN, an AlGaN, a GaN, an InN, an InGaN, an AlInN, an AlInGaN, or a BN material.

14. The method of claim 11 wherein at least one of the one or more second piezoelectric layers comprises an AlN, an AlGaN, a GaN, an InN, an InGaN, an AlInN, an AlInGaN, or a BN material.

15. The method of claim 11 wherein forming the first device comprises a forming passive device, a filter device, a switch device, an amplifier device, or an acoustic resonator device.

16. The method of claim 11 wherein forming the second device comprises forming a switch device, an antenna switch module, a filter device, an amplifier device, a low noise amplifier device, a power amplifier device, a power amplifier duplexer device, a passive device, or an active device.

17. The method of claim 11 further comprising forming a cap layer overlying the one or more second piezoelectric layers.

18. The method of claim 17 wherein the cap layer comprises a silicon, a sapphire, a silicon carbide, a GaN bulk, a GaN template, an AlN bulk, an AlN template, or an Al x Ga 1-x N template material.

19. The method of claim 17 wherein forming the second device includes forming the second device overlying the cap layer.

20. The method of claim 17 wherein the first piezoelectric layer is characterized by a thickness of about 0.01 um to about 10.0 um;

wherein at least one the one or more second piezoelectric layers is characterized by a thickness ranging from about 10 nm to about 1200 nm; and

wherein the cap layer is characterized by a thickness ranging from about 0.10 nm to about 5.0 nm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2025
From: AKOUSTIS TECHNOLOGIES, INC.; AKOUSTIS, INC.; RFM INTEGRATED DEVICE INC.
To: TUNE HOLDINGS CORP.
Reel/Frame 071577/0095 →
CHANGE OF NAME Recorded Jul 1, 2025
From: TUNE HOLDINGS CORP.
To: AKOUSTIS TECHNOLOGIES CORP.
Reel/Frame 071782/0462 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021
From: GIBB, SHAWN R.; AICHELE, DAVID; VETURY, RAMAKRISHNA; BOOMGARDEN, MARK D.; SHEALY, JEFFREY B.
To: AKOUSTIS, INC.
Reel/Frame 055352/0601 →
Continuity (3)
Continuation 16532333 · Aug 5, 2019
Continuation 15405167 · Jan 12, 2017
Related Publication 20210202473A1 · Jul 1, 2021