IP Library Granted Patent US 11,423,931
Granted Patent B2
US 11,423,931 · App. 17/180,806 · Granted Aug 23, 2022

Data storage device interleave driving secondary actuators

Inventors: Kevin Tzou (San Jose, CA); Robert C. Reinhart (San Jose, CA); Hitoshi Shindo (San Jose, CA); Shigenori Takada (Kawasaki, JP)
Assignee: Western Digital Technologies, Inc.
G11B5/5552G11B5/4873
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Quick Facts
Patent No.
US 11,423,931
App. No.
17/180,806
Granted
Aug 23, 2022
Kind
B2
Abstract

A data storage device is disclosed comprising a plurality of disks each comprising a top disk surface and a bottom disk surface, and a plurality of actuator arms each comprising a first fine actuator configured to actuate a top head over one of the top disk surfaces and a second fine actuator configured to actuate a bottom head over one of the bottom disk surfaces. A first fine driver controls the fine actuators of an even interleave of the actuator arms, and a second fine driver controls the fine actuators of an odd interleave of the actuator arms.

Claims (55)

1. A data storage device comprising:

a plurality of disks each comprising a top disk surface and a bottom disk surface;

a plurality of actuator arms each comprising a first fine actuator configured to actuate a top head over one of the top disk surfaces and a second fine actuator configured to actuate a bottom head over one of the bottom disk surfaces;

a coarse actuator configured to concurrently move the actuator arms to actuate the top and bottom heads over respective top and bottom disk surfaces;

a first driver configured to drive the first and second fine actuators of an even interleave of the actuator arms, wherein the first driver is configured to:

apply a first control signal to the first fine actuators of the even interleave of the actuator arms, and

apply a second control signal to the second fine actuators of the even interleave of the actuator arms, the second control signal having an opposite polarity of the first control signal; and

a second driver configured to drive the first and second fine actuators of an odd interleave of the actuator arms independent of the first driver driving the first and second fine actuators of the even interleave of the actuator arms, wherein the second driver is configured to:

apply a third control signal to the first fine actuators of the odd interleave of the actuator arms, and

apply a fourth control signal to the second fine actuators of the odd interleave of the actuator arms, the fourth control signal having an opposite polarity of the third control signal.

2. The data storage device as recited in claim 1 , wherein driving the first and second fine actuators of interleaved actuator arms using the first and second drivers attenuates a vibration mode of the actuator arms.

3. The data storage device as recited in claim 1 , further comprising control circuitry configured to:

control the first driver based on first servo data read from a top disk surface of a first disk in order to access the top disk surface of the first disk using the respective top head; and

control the second driver based on second servo data read from a bottom disk surface of the first disk in order to access the bottom disk surface of the first disk surface using the respective bottom head.

4. The data storage device of claim 1 , wherein the second control signal is generated by inverting the first control signal, and the fourth control signal is generated by inverting the third control signal.

5. The data storage device of claim 4 , wherein the inversion is conducted using an analog converter.

6. The data storage device of claim 4 , wherein the inversion is conducted using a non-inverting amplifier having a first gain and an inverting amplifier having a second gain equal to the first gain.

7. The data storage device of claim 1 , further comprising control circuitry configured to:

access the top disk surface of a first disk using the top head coupled to the second fine actuator of a first actuator arm of the even interleave; and

concurrently with the accessing of the top disk surface of the first disk, access the bottom disk surface of the first disk using the bottom head coupled to the first fine actuator of a first actuator arm of the odd interleave.

8. The data storage device of claim 7 , wherein the control circuitry is further configured to:

access the top disk surface of a second disk using the top head coupled to the second fine actuator of the first actuator arm of the odd interleave; and

concurrently with the accessing of the top disk surface of the second disk, access the bottom disk surface of the second disk using the bottom head coupled to the first fine actuator of a second actuator arm of the even interleave.

9. Control circuitry comprising:

a first driver configured to drive a first fine actuator and a second fine actuator of each actuator arm of an even interleave of a plurality of actuator arms, wherein the first driver is configured to:

apply a first control signal to the first fine actuators of the even interleave of the actuator arms; and

apply a second control signal to the second fine actuators of the even interleave of the actuator arms, the second control signal having an opposite polarity of the first control signal; and

a second driver configured to drive a first fine actuator and a second fine actuator of each actuator arm of an odd interleave of the actuator arms independent of the first driver driving the first and second fine actuators of the even interleave of the actuator arms, wherein the second driver is configured to:

apply a third control signal to the first fine actuators of the odd interleave of the actuator arms; and

apply a fourth control signal to the second fine actuators of the odd interleave of the actuator arms, the fourth control signal having an opposite polarity of the third control signal.

10. The control circuitry of claim 9 , wherein the second control signal is generated by inverting the first control signal, and the fourth control signal is generated by inverting the third control signal.

11. The control circuitry of claim 10 , wherein the inversion is conducted using an analog converter.

12. The control circuitry of claim 10 , wherein the inversion is conducted using a non-inverting amplifier having a first gain and an inverting amplifier having a second gain equal to the first gain.

13. The control circuitry of claim 9 , wherein the control circuitry is configured to:

access a top disk surface of a first disk using a head coupled to the second fine actuator of a first actuator arm of the even interleave; and

concurrently with the accessing of the top disk surface of the first disk, access a bottom disk surface of the first disk using a head coupled to the first fine actuator of a first actuator arm of the odd interleave.

14. The control circuitry of claim 13 , wherein the control circuitry is further configured to:

access a top disk surface of a second disk using a head coupled to the second fine actuator of the first actuator arm of the odd interleave; and

concurrently with the accessing of the top disk surface of the second disk, access a bottom disk surface of the second disk using a head coupled to the first fine actuator of a second actuator arm of the even interleave.

15. Control circuitry comprising:

a first means for driving a first fine actuator and a second fine actuator of each actuator arm of an even interleave of a plurality of actuator arms, the first means comprising:

a means for applying a first control signal to the first fine actuators of the even interleave of the actuator arms, and

a means for applying a second control signal to the second fine actuators of the even interleave of the actuator arms, the second control signal having an opposite polarity of the first control signal; and

a second means for driving a first fine actuator and a second fine actuator of each actuator arm of an odd interleave of the actuator arms independent of the first driver means driving the first and second fine actuators of the even interleave of the actuator arms, the second means comprising:

a means for applying a third control signal to the first fine actuators of the odd interleave of the actuator arms, and

a means for applying a fourth control signal to the second fine actuators of the odd interleave of the actuator arms, the fourth control signal having an opposite polarity of the third control signal.

16. The control circuitry of claim 15 , wherein the second control signal is generated by inverting the first control signal, and the fourth control signal is generated by inverting the third control signal.

17. The control circuitry of claim 16 , wherein the inversion is conducted using an analog converter.

18. The control circuitry of claim 16 , wherein the inversion is conducted using a non-inverting amplifier having a first gain and an inverting amplifier having a second gain equal to the first gain.

19. The control circuitry of claim 15 , wherein the control circuitry is configured to:

access a top disk surface of a first disk using a head coupled to the second fine actuator of a first actuator arm of the even interleave; and

concurrently with the accessing of the top disk surface of the first disk, access a bottom disk surface of the first disk using a head coupled to the first fine actuator of a first actuator arm of the odd interleave.

20. The control circuitry of claim 19 , wherein the control circuitry is further configured to:

access a top disk surface of a second disk using a head coupled to the second fine actuator of the first actuator arm of the odd interleave; and

concurrently with the accessing of the top disk surface of the second disk, access a bottom disk surface of the second disk using a head coupled to the first fine actuator of a second actuator arm of the even interleave.

Assignments (5)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2021
From: TZOU, KEVIN; REINHART, ROBERT C.; SHINDO, HITOSHI; TAKADA, SHIGENORI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055346/0546 →
Continuity (2)
Provisional Application 63113837 · Nov 14, 2020
Related Publication 20220157338A1 · May 19, 2022